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Chang Hua Siau

age ~49

from Saratoga, CA

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Also known as:
  • Chang H Siau
  • Chang Bernadine Siau
  • Chang N Siau
  • Saiu Chang
Phone and address:
18437 Mccoy Ave, Saratoga, CA 95070
Related to:
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Chang Siau Phones & Addresses

  • 18437 Mccoy Ave, Saratoga, CA 95070
  • Santa Clara, CA
  • San Jose, CA
  • Ames, IA

Us Patents

  • Sensing A Signal In A Two-Terminal Memory Array Having Leakage Current

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  • US Patent:
    7379364, May 27, 2008
  • Filed:
    Oct 19, 2006
  • Appl. No.:
    11/583446
  • Inventors:
    Chang Hua Siau - San Jose CA, US
    Christophe Chevallier - Palo Alto CA, US
    Darrell Rinerson - Cupertino CA, US
  • International Classification:
    G11C 7/02
  • US Classification:
    365209, 365158, 365171
  • Abstract:
    A two-terminal memory array includes a plurality of first and second conductive traces. An address unit operatively applies a select voltage across a selected pair of the first and second conductive traces and applies a non-select voltage potential to unselected traces. A total current flowing in the selected first conductive trace and a leakage current flowing through unselected second conductive traces are sensed by a sense unit in a one cycle or a two cycle pre-read operation. The total and leakage currents can be combined with a reference signal to derive a data signal indicative of one of a plurality of conductivity profiles that represent stored data. The conductivity profiles can be stored in a resistive state memory element that is electrically in series with the selected first and second conductive traces.

  • Method For Two-Cycle Sensing In A Two-Terminal Memory Array Having Leakage Current

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  • US Patent:
    7436723, Oct 14, 2008
  • Filed:
    Mar 3, 2008
  • Appl. No.:
    12/074448
  • Inventors:
    Darrell Rinerson - Cupertino CA, US
    Christophe J. Chevallier - Palo Alto CA, US
    Chang Hua Siau - San Jose CA, US
  • International Classification:
    G11C 7/02
  • US Classification:
    365209, 365148, 365158
  • Abstract:
    A two-terminal memory array includes a plurality of first and second conductive traces. An address unit operatively applies a select voltage across a selected pair of the first and second conductive traces and applies a non-select voltage potential to unselected traces. A total current flowing in the selected first conductive trace and a leakage current flowing through unselected second conductive traces are sensed by a sense unit in a one cycle or a two cycle pre-read operation. The total and leakage currents can be combined with a reference signal to derive a data signal indicative of one of a plurality of conductivity profiles that represent stored data. The conductivity profiles can be stored in a resistive state memory element that is electrically in series with the selected first and second conductive traces.

  • Method For Sensing A Signal In A Two-Terminal Memory Array Having Leakage Current

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  • US Patent:
    7505347, Mar 17, 2009
  • Filed:
    Feb 28, 2008
  • Appl. No.:
    12/072813
  • Inventors:
    Darrell Rinerson - Cupertino CA, US
    Christophe J. Chevallier - Palo Alto CA, US
    Chang Hua Siau - San Jose CA, US
  • Assignee:
    Unity Semiconductor Corporation - Sunnyvale CA
  • International Classification:
    G11C 7/02
  • US Classification:
    365209, 365148, 365158
  • Abstract:
    A two-terminal memory array includes a plurality of first and second conductive traces. An address unit operatively applies a select voltage across a selected pair of the first and second conductive traces and applies a non-select voltage potential to unselected traces. A total current flowing in the selected first conductive trace and a leakage current flowing through unselected second conductive traces are sensed by a sense unit in a one cycle or a two cycle pre-read operation. The total and leakage currents can be combined with a reference signal to derive a data signal indicative of one of a plurality of conductivity profiles that represent stored data. The conductivity profiles can be stored in a resistive state memory element that is electrically in series with the selected first and second conductive traces.

  • Low Read Current Architecture For Memory

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  • US Patent:
    7701791, Apr 20, 2010
  • Filed:
    Jul 26, 2007
  • Appl. No.:
    11/881500
  • Inventors:
    Darrell Rinerson - Cupertino CA, US
    Christophe J. Chevallier - Palo Alto CA, US
    Chang Hua Siau - San Jose CA, US
  • International Classification:
    G11C 7/00
  • US Classification:
    365203, 365148, 365205
  • Abstract:
    A low read current architecture for memory. Bit lines of a cross point memory array are allowed to be charged by a selected word line until a minimum voltage differential between a memory state and a reference level is assured.

  • Contemporaneous Margin Verification And Memory Access For Memory Cells In Cross Point Memory Arrays

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  • US Patent:
    7830701, Nov 9, 2010
  • Filed:
    Sep 19, 2008
  • Appl. No.:
    12/284227
  • Inventors:
    Chang Hua Siau - San Jose CA, US
    Christophe J. Chevallier - Palo Alto CA, US
  • International Classification:
    G11C 11/00
  • US Classification:
    365148, 36518907
  • Abstract:
    Circuitry and methods for restoring data values in non-volatile memory are disclosed. An integrated circuit includes a memory access circuit and a sensing circuit configured to sense a data signal during a read operation to at least one two-terminal non-volatile cross-point memory array. Each memory array includes a plurality of two-terminal memory cells. A plurality of the memory arrays can be fabricated over the substrate and vertically stacked on one another. Further, the integrated circuit can include a margin manager circuit configured to manage a read margin for the two-terminal memory cells substantially during the read operation, thereby providing for contemporaneous read and margin determination operations. Stored data read from the two-terminal memory cells may have a value of the stored data restored (e. g. , re-written to the same cell or another cell) if the value is not associated with a read margin (e. g.

  • Method For Contemporaneous Margin Verification And Memory Access For Memory Cells In Cross-Point Memory Arrays

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  • US Patent:
    7978501, Jul 12, 2011
  • Filed:
    Nov 9, 2010
  • Appl. No.:
    12/927247
  • Inventors:
    Christophe Chevallier - Palo Alto CA, US
    Chang Hua Siau - Saratoga CA, US
  • International Classification:
    G11C 11/00
  • US Classification:
    365148, 3651852, 36518907
  • Abstract:
    Circuitry and methods for restoring data values in non-volatile memory are disclosed. An integrated circuit includes a memory access circuit and a sensing circuit configured to sense a data signal during a read operation to at least one two-terminal non-volatile cross-point memory array. Each memory array includes a plurality of two-terminal memory cells. A plurality of the memory arrays can be fabricated over the substrate and vertically stacked on one another. Further, the integrated circuit can include a margin manager circuit configured to manage a read margin for the two-terminal memory cells substantially during the read operation, thereby providing for contemporaneous read and margin determination operations. Stored data read from the two-terminal memory cells may have a value of the stored data restored (e. g. , re-written to the same cell or another cell) if the value is not associated with a read margin (e. g.

  • Two-Cycle Sensing In A Two-Terminal Memory Array Having Leakage Current

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  • US Patent:
    7372753, May 13, 2008
  • Filed:
    Oct 19, 2006
  • Appl. No.:
    11/583676
  • Inventors:
    Darrell Rinerson - Cupertino CA, US
    Christophe Chevallier - Palo Alto CA, US
    Chang Hua Siau - San Jose CA, US
  • International Classification:
    G11C 7/02
  • US Classification:
    365209, 365 51, 365 63, 365148
  • Abstract:
    A two-terminal memory array includes a plurality of first and second conductive traces. An address unit operatively applies a select voltage across a selected pair of the first and second conductive traces and applies a non-select voltage potential to unselected traces. A total current flowing in the selected first conductive trace and a leakage current flowing through unselected second conductive traces are sensed by a sense unit in a one cycle or a two cycle pre-read operation. The total and leakage currents can be combined with a reference signal to derive a data signal indicative of one of a plurality of conductivity profiles that represent stored data. The conductivity profiles can be stored in a resistive state memory element that is electrically in series with the selected first and second conductive traces.

  • Low Read Current Architecture For Memory

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  • US Patent:
    8031545, Oct 4, 2011
  • Filed:
    Apr 19, 2010
  • Appl. No.:
    12/799168
  • Inventors:
    Darrell Rinerson - Cupertino CA, US
    Christophe Chevallier - Palo Alto CA, US
    Chang Hua Siau - Saratoga CA, US
  • International Classification:
    G11C 7/00
  • US Classification:
    365203, 365148, 36523003
  • Abstract:
    A low read current architecture for memory. Bit lines of a cross point memory array are allowed to be charged by a selected word line until a minimum voltage differential between a memory state and a reference level is assured.
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