Chad S Gallun

Address:

6023 Bel Fay Ln, Austin, TX 78749

VIN:

5FNRL386X7B028764

Make:

HONDA

Model:

ODYSSEY

Year:

2007

US Patent:

57544824, May 19, 1998

Filed:

Apr 21, 1997

Appl. No.:

8/845097

Inventors:

Jeffrey Yangming Su - Cedar Park TX
Bruce Lee Morton - Austin TX
Chad Steven Gallun - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G11C 1604

US Classification:

36518907

Abstract:

A memory (400) returns all bit lines to a predetermined voltage level optimum for subsequent fast sensing. The memory (400) includes precharge circuitry (106, 108, 110) which begins the precharge operation during the latching phase of a prior access. The precharge circuitry (106, 108, 110) precharges all bit lines, rather than a selected bit line, to the predetermined voltage level prior to address decoding. In order to prevent "walk-up", the memory (400) includes circuitry such as a switched capacitor (138, 140) which draws current from the bit lines to reduce the voltage on a bit line which drove a logic high level in an earlier cycle or which had an increased voltage due to capacitive cross-coupling to an adjacent bit line. The memory (400) may also include devices such as transmission gates (142, 144, 146) to couple together adjacent bit lines and thereby more evenly distribute the precharging.

US Patent:

20210111861, Apr 15, 2021

Filed:

Dec 21, 2020

Appl. No.:

17/128720

Inventors:

- Santa Clara CA, US
- Markham, CA
Gerald R. Talbot - Boxborough MA, US
Gurunath Dollin - Santa Clara CA, US
Damon Tohidi - Markham, CA
Eric Ian Carpenter - Fort Collins CO, US
Chad S. Gallun - Austin TX, US
Jeffrey Cooper - Fort Collins CO, US
Hanwoo Cho - Santa Clara CA, US
Scott F. Dow - Fruita CO, US
Michael J. Tresidder - Austin TX, US

International Classification:

H04L 7/04
H04L 7/00

Abstract:

Systems, apparatuses, and methods for implementing a deskewing method for a physical layer interface on a multi-chip module are disclosed. A circuit connected to a plurality of communication lanes trains each lane to synchronize a local clock of the lane with a corresponding global clock at a beginning of a timing window. Next, the circuit symbol rotates each lane by a single step responsive to determining that all of the plurality of lanes have an incorrect symbol alignment. Responsive to determining that some but not all of the plurality of lanes have a correct symbol alignment, the circuit symbol rotates lanes which have an incorrect symbol alignment by a single step. When the end of the timing window has been reached, the circuit symbol rotates lanes which have a correct symbol alignment and adjusts a phase of a corresponding global clock to compensate for missed symbol rotations.

US Patent:

20200344039, Oct 29, 2020

Filed:

Dec 10, 2019

Appl. No.:

16/709472

Inventors:

- Santa Clara CA, US
- Markham CA, US
Gerald R. Talbot - Concord MA, US
Gurunath Dollin - San Jose CA, US
Damon Tohidi - Richmond Hill, CA
Eric Ian Carpenter - Fort Collins CO, US
Chad S. Gallun - Austin TX, US
Jeffrey Cooper - Fort Collins CO, US
Hanwoo Cho - San Diego CA, US
Scott F. Dow - Fruita CO, US
Michael J. Tresidder - Spicewood TX, US

International Classification:

H04L 7/04
H04L 7/00

Abstract:

Systems, apparatuses, and methods for implementing a deskewing method for a physical layer interface on a multi-chip module are disclosed. A circuit connected to a plurality of communication lanes trains each lane to synchronize a local clock of the lane with a corresponding global clock at a beginning of a timing window. Next, the circuit symbol rotates each lane by a single step responsive to determining that all of the plurality of lanes have an incorrect symbol alignment. Responsive to determining that some but not all of the plurality of lanes have a correct symbol alignment, the circuit symbol rotates lanes which have an incorrect symbol alignment by a single step. When the end of the timing window has been reached, the circuit symbol rotates lanes which have a correct symbol alignment and adjusts a phase of a corresponding global clock to compensate for missed symbol rotations.

US Patent:

20200099406, Mar 26, 2020

Filed:

Sep 24, 2018

Appl. No.:

16/140364

Inventors:

- Santa Clara CA, US
Milam Paraschou - Dellwood MN, US
Chad S. Gallun - Austin TX, US
Jeffrey Cooper - Fort Collins CO, US
Dean E. Gonzales - Fort Collins CO, US
Alushulla Jack Ambundo - Austin TX, US
Gerald R. Talbot - Concord MA, US

International Classification:

H04B 1/04
H04B 1/16
H01L 27/02
H03M 1/80

Abstract:

Systems, apparatuses, and methods for performing efficient data transfer in a computing system are disclosed. A computing system includes multiple transmitters sending singled-ended data signals to multiple receivers. A termination voltage is generated and sent to the multiple receivers. The termination voltage is coupled to each of signal termination circuitry and signal sampling circuitry within each of the multiple receivers. Any change in the termination voltage affects the termination circuitry and affects comparisons performed by the sampling circuitry. Received signals are reconstructed at the receivers using the received signals, the signal termination circuitry and the signal sampling circuitry.