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Burton B Lo

age ~54

from San Francisco, CA

Also known as:
  • Burton Sophine Lo
  • Burton Sophina Lo
  • Burton Chilton Lina Lo
  • Burton L Lo
  • Burton Sophia Lo
  • Burton Bo Shenglo
  • Loburton Bs
  • Bo Lo Burton
Phone and address:
1085 Holloway Ave, San Francisco, CA 94132
415-640-8967

Burton Lo Phones & Addresses

  • 1085 Holloway Ave, San Francisco, CA 94132 • 415-640-8967
  • 1739 38Th Ave, San Francisco, CA 94122 • 415-759-8919
  • 1083 Holloway Ave, San Francisco, CA 94132
  • Lombard, IL
  • Berkeley, CA
  • 1085 Holloway Ave, San Francisco, CA 94132 • 415-640-7983

Work

  • Company:
    Velodyne lidar, inc.
    Feb 2019
  • Position:
    Principal fpga verification engineer

Education

  • Degree:
    Bachelors, Bachelor of Science
  • School / High School:
    University of California, Berkeley
    1994
  • Specialities:
    Electrical Engineering, Computer Science

Skills

Asic • Verilog • Fpga • Debugging • Simulations • Soc • Testing • Systemverilog • Rtl Design • Ethernet • Application Specific Integrated Circuits • Vhdl • Analog • Field Programmable Gate Arrays • Uvm • Functional Verification • Perl • Python • Integrated Circuits • Computer Networking • Computer Graphics • Telecom • Scripting • Rtl Verification • Rtl Coding

Emails

b***1@nad.3com.com

Industries

Computer Hardware
Name / Title
Company / Classification
Phones & Addresses
Burton Lo
President
ZIOM CORPORATION
1085 Holloway Ave, San Francisco, CA 94132

Resumes

Burton Lo Photo 1

Principal Fpga Verification Engineer

view source
Location:
San Francisco, CA
Industry:
Computer Hardware
Work:
Velodyne Lidar, Inc.
Principal Fpga Verification Engineer

Facebook Nov 2017 - Apr 2018
Verification Engineer

Imagination Technologies Dec 2010 - Sep 2017
Senior Hardware Engineer

Caustic Graphics May 2008 - Dec 2010
Verification Engineer

Burton Lo Engineering Feb 2006 - Apr 2008
Asic and Fpga Verification Consultant
Education:
University of California, Berkeley 1994
Bachelors, Bachelor of Science, Electrical Engineering, Computer Science
Skills:
Asic
Verilog
Fpga
Debugging
Simulations
Soc
Testing
Systemverilog
Rtl Design
Ethernet
Application Specific Integrated Circuits
Vhdl
Analog
Field Programmable Gate Arrays
Uvm
Functional Verification
Perl
Python
Integrated Circuits
Computer Networking
Computer Graphics
Telecom
Scripting
Rtl Verification
Rtl Coding

Us Patents

  • Low Power Buffer System For Network Communications

    view source
  • US Patent:
    6341135, Jan 22, 2002
  • Filed:
    Feb 26, 1998
  • Appl. No.:
    09/032382
  • Inventors:
    Marwan A. Fawal - Santa Clara CA
    Burton B. Lo - San Francisco CA
    Anthony L. Pan - Fremont CA
  • Assignee:
    3Com Corporation - Santa Clara CA
  • International Classification:
    G01R 1900
  • US Classification:
    370419, 327108
  • Abstract:
    NMOS transistor buffers are used to buffer the output of a system. The system can include a network interface card. The NMOS transistor buffers receive the output of the shaped Ethernet data signals and drive a transformer. The NMOS transistor buffers allow for low power consumption while a feedback monitoring system provides stability by controlling the inputs to the NMOS transistors.
  • Fifo Queued Entry Point Circuit For A Network Interface Card

    view source
  • US Patent:
    6360278, Mar 19, 2002
  • Filed:
    May 27, 1999
  • Appl. No.:
    09/321307
  • Inventors:
    Burton B. Lo - San Francisco CA
    Krishna Uppunda - Santa Clara CA
    Anthony L. Pan - Fremont CA
  • Assignee:
    3COM Corporation - Santa Clara CA
  • International Classification:
    G06F 1300
  • US Classification:
    709250, 709231, 709232, 709233, 710 5
  • Abstract:
    A first-in-first-out (FIFO) entry point circuit for a network interface card. The novel circuit of the present invention provides a FIFO entry point circuit within a network interface card (NIC). The FIFO implementation allows multiple downlist pointers to be maintained within the transmit (Tx) FIFO entry point circuit and also allows multiple uplist pointers to be maintained for the receive (Rx) FIFO entry point circuit. For the Tx FIFO entry point circuit, only one register is visible to the processor which can load a memory pointer into the entry point thereby placing the memory pointer on the bottom on the FIFO. Only one register is seen for the Rx FIFO entry point circuit. With respect to the Tx FIFO entry point circuit, the NIC takes the oldest entry, obtains the packet from memory that is indicated by the corresponding pointer and transmits the packet onto a network. If the packet points to a next packet, then that next packet is sent, otherwise the next pointer of the Tx FIFO entry point is then processed by the NIC. Signals indicate when the Rx or Tx FIFO entry points are full.
  • Slave Interface Circuit For Providing Communication Between A Peripheral Component Interconnect (Pci) Domain And An Advanced System Bus (Asb)

    view source
  • US Patent:
    6366973, Apr 2, 2002
  • Filed:
    May 3, 1999
  • Appl. No.:
    09/304034
  • Inventors:
    Burton B. Lo - San Francisco CA
    Anthony L. Pan - Fremont CA
  • Assignee:
    3COM Corporation - Santa Clara CA
  • International Classification:
    G06F 1340
  • US Classification:
    710128, 710129
  • Abstract:
    A slave interface circuit for providing communication between a PCI (Peripheral Component Interconnect) bus domain and an ASB (Advanced System Bus) bus domain. The novel circuit is an integrated interface for communicating using the AMBA (Advanced Microcontroller Bus Architecture) ASB protocol and translating ASB commands into PCI like commands. Embodiments include interfaces that are particularly suited for FPGA (field programmable gate array) and ASIC (application specific integrated circuit) implementations. A high-speed embodiment is also discussed allowing prefetch functionality. Input latches catch ASB commands on the falling edge of the ASB clock and then circuits reformat the data using size information and address bits from the ASB bus. This allows byte, halfword and word accesses. Byte readback data are provided on all four byte lanes and halfword readback data are provided on both halfword lanes.
  • Subsystem Bridge Of Ambas Asb Bus To Peripheral Component Interconnect (Pci) Bus

    view source
  • US Patent:
    6425071, Jul 23, 2002
  • Filed:
    May 3, 1999
  • Appl. No.:
    09/303890
  • Inventors:
    Burton B. Lo - San Francisco CA
    Anthony L. Pan - Fremont CA
  • Assignee:
    3COM Corporation - Santa Clara CA
  • International Classification:
    G06F 1300
  • US Classification:
    712 41, 712 38
  • Abstract:
    A method and apparatus to bridge between the PCI bus and a RISC processor interface bus. In one embodiment, the present invention is a single-ASIC implementation rather than a design using multiple discrete circuit components. The invention incorporates a method and apparatus that will minimize subsystem latencies and inefficiencies in order to maximize data throughput and system performance. In yet another embodiment, the RISC processor interface bus is the AMBA ASB bus. The invention further provides an Advanced RISC Machine interface bus unit which uses an improved clock crossing handshake mechanism that can support a range of clock frequencies on the AMBA ASB bus.
  • System And Method To Reduce Electromagnetic Interference Emissions In A Network Interface

    view source
  • US Patent:
    6452938, Sep 17, 2002
  • Filed:
    Feb 26, 1998
  • Appl. No.:
    09/031265
  • Inventors:
    Marwan A. Fawal - Santa Clara CA
    Burton B. Lo - San Francisco CA
    Anthony L. Pan - Fremont CA
    George Kwan - Sunnyvale CA
  • Assignee:
    3Com Corporation - Santa Clara CA
  • International Classification:
    H04L 1266
  • US Classification:
    370463
  • Abstract:
    A system for reducing electromagnetic interference emissions is described. The system can include a network interface card with an Ethernet controller circuit. The Ethernet controller circuit generates an Ethernet output signal that includes a pre-emphasis component and a data component. The Ethernet controller circuit monitors the Ethernet output signal and adjusts the levels of the pre-emphasis component and the data component to reduce the electromagnetic interference caused by the network interface card but still fit the requirements for valid Ethernet signals.
  • Scaleable Priority Arbiter For Arbitrating Between Multiple Fifo Entry Points Of A Network Interface Card

    view source
  • US Patent:
    6667983, Dec 23, 2003
  • Filed:
    May 27, 1999
  • Appl. No.:
    09/321068
  • Inventors:
    Burton B. Lo - San Francisco CA
    Krishna Uppunda - Santa Clara CA
    Anthony L. Pan - Fremont CA
  • Assignee:
    3Com Corporation - Santa Clara CA
  • International Classification:
    H04L 1228
  • US Classification:
    370412, 370428
  • Abstract:
    A scaleable priority arbiter for arbitrating between multiple FIFO entry points of a network interface card (NIC). The circuit provides a separate FIFO entry point circuit within the NIC for each data packet priority type. Exemplary priority types, from highest to lowest, include isochronous, priority , priority ,. . . , priority n. A separate set of FIFO entry points are provided for NIC transmitting (Tx) and for NIC receiving (Rx). For each of the Tx FIFO entry points, a single Tx entry point register is seen by the processor and multiple downlist pointers are also maintained. The Tx entry point registers all feed a scaleable priority arbiter which selects the next message for transmission. The scaleable priority arbiter is made of scaleable circuit units that contain a sequential element controlling a multiplexer. The multiplexer selects between two inputs, a first input is dedicated to data packets of the priority type corresponding to the circuit stage and the other input comes from the lower priority chain.
  • Telephone Network Signal Conversion System

    view source
  • US Patent:
    6801605, Oct 5, 2004
  • Filed:
    Sep 13, 2000
  • Appl. No.:
    09/660825
  • Inventors:
    George Kwan - Sunnyvale CA
    Maria B. Hu - San Jose CA
    Burton B. Lo - San Francisco CA
    Anthony Pan - Fremont CA
  • Assignee:
    3Com Corporation - Santa Clara CA
  • International Classification:
    H04M 1100
  • US Classification:
    379 9315, 379 9305, 379 9306, 37938702, 37939201
  • Abstract:
    An integrated circuit is provided to convert an analog telephone signal into a digital format. The integrated circuit includes an analog-digital converter coupled to an averager. Sampled analog values are averaged at intervals and compared to a threshold level to determine a digital value.
  • Current Controlled Oscillator With Voltage Independent Capacitance

    view source
  • US Patent:
    57932603, Aug 11, 1998
  • Filed:
    Apr 26, 1996
  • Appl. No.:
    8/641101
  • Inventors:
    Marwan A. Fawal - Santa Clara CA
    Burton B. Lo - San Francisco CA
    Ruchi Wadhawan - Sunnyvale CA
  • Assignee:
    3Com Corporation - Santa Clara CA
  • International Classification:
    H01G 9048
    H03L 7085
  • US Classification:
    331111
  • Abstract:
    A current-controlled oscillator with first and second differential comparators (640, 840) serving as inputs, first and second voltage independent multi-layered integrated capacitors (600, 800) corresponding to the first and second comparators (640, 840), and a RS latch (700) for switching operation between the two comparators (640, 840) thereby achieving oscillation. The multi-layered integrated capacitors (600, 800) are designed to provide voltage independent capacitance.

Googleplus

Burton Lo Photo 2

Burton Lo

Tagline:
I am a technology consultant, project manager, photographer, counselor, coach, and father.
Burton Lo Photo 3

Burton Lo

Facebook

Burton Lo Photo 4

Burt Lo

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Burton Lo

Youtube

Lo Shu / Solfeggio code. 9 stack mountain c5 ...

Light-Dark male-female, -odd even, and all myraid of creatures follow....

  • Category:
    Science & Technology
  • Uploaded:
    04 Mar, 2011
  • Duration:
    10m 8s

Lo Shu / Solfeggio code found in 123 Field ''...

PLEASE NOTE: PLANE ANALYSIS IS GOOD FOR ALL + - PERP FIELDS. This is n...

  • Category:
    Science & Technology
  • Uploaded:
    05 Mar, 2010
  • Duration:
    5m 19s

pasodoble cantado a tenor por las locuras de ...

pasodoble cantado a tenor por las locuras de martin burton en la gala ...

  • Category:
    Music
  • Uploaded:
    08 May, 2011
  • Duration:
    1m 59s

" Vincent " By Tim Burton

cortometraje al estilo "the nightmare b4 xmas" o "the corpes bride"......

  • Category:
    Film & Animation
  • Uploaded:
    01 Mar, 2007
  • Duration:
    5m 52s

Big Trouble In Little China Remix

btilc Jack Burton Vs David Lo Pan The Peter KWong Dance Lightning show...

  • Category:
    Music
  • Uploaded:
    12 Jan, 2010
  • Duration:
    3m 6s

LO MEJOR DE TIM BURTON

las mejores peliculas de tim burton

  • Category:
    Entertainment
  • Uploaded:
    30 May, 2010
  • Duration:
    4m 10s

Sabes lo que dice Jack Burton?

Escena de la pelcula golpe en la pequea china. Dirigida por John Carpe...

  • Category:
    Film & Animation
  • Uploaded:
    20 Feb, 2010
  • Duration:
    43s

Si supieras lo que sufro. Las Locuras de Mart...

Pasodoble de la comparsa de Antonio Martn "Las Locuras de Martn Burton...

  • Category:
    Music
  • Uploaded:
    18 Feb, 2011
  • Duration:
    2m 7s

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