Marwan A. Fawal - Santa Clara CA Burton B. Lo - San Francisco CA Anthony L. Pan - Fremont CA
Assignee:
3Com Corporation - Santa Clara CA
International Classification:
G01R 1900
US Classification:
370419, 327108
Abstract:
NMOS transistor buffers are used to buffer the output of a system. The system can include a network interface card. The NMOS transistor buffers receive the output of the shaped Ethernet data signals and drive a transformer. The NMOS transistor buffers allow for low power consumption while a feedback monitoring system provides stability by controlling the inputs to the NMOS transistors.
Fifo Queued Entry Point Circuit For A Network Interface Card
Burton B. Lo - San Francisco CA Krishna Uppunda - Santa Clara CA Anthony L. Pan - Fremont CA
Assignee:
3COM Corporation - Santa Clara CA
International Classification:
G06F 1300
US Classification:
709250, 709231, 709232, 709233, 710 5
Abstract:
A first-in-first-out (FIFO) entry point circuit for a network interface card. The novel circuit of the present invention provides a FIFO entry point circuit within a network interface card (NIC). The FIFO implementation allows multiple downlist pointers to be maintained within the transmit (Tx) FIFO entry point circuit and also allows multiple uplist pointers to be maintained for the receive (Rx) FIFO entry point circuit. For the Tx FIFO entry point circuit, only one register is visible to the processor which can load a memory pointer into the entry point thereby placing the memory pointer on the bottom on the FIFO. Only one register is seen for the Rx FIFO entry point circuit. With respect to the Tx FIFO entry point circuit, the NIC takes the oldest entry, obtains the packet from memory that is indicated by the corresponding pointer and transmits the packet onto a network. If the packet points to a next packet, then that next packet is sent, otherwise the next pointer of the Tx FIFO entry point is then processed by the NIC. Signals indicate when the Rx or Tx FIFO entry points are full.
Slave Interface Circuit For Providing Communication Between A Peripheral Component Interconnect (Pci) Domain And An Advanced System Bus (Asb)
Burton B. Lo - San Francisco CA Anthony L. Pan - Fremont CA
Assignee:
3COM Corporation - Santa Clara CA
International Classification:
G06F 1340
US Classification:
710128, 710129
Abstract:
A slave interface circuit for providing communication between a PCI (Peripheral Component Interconnect) bus domain and an ASB (Advanced System Bus) bus domain. The novel circuit is an integrated interface for communicating using the AMBA (Advanced Microcontroller Bus Architecture) ASB protocol and translating ASB commands into PCI like commands. Embodiments include interfaces that are particularly suited for FPGA (field programmable gate array) and ASIC (application specific integrated circuit) implementations. A high-speed embodiment is also discussed allowing prefetch functionality. Input latches catch ASB commands on the falling edge of the ASB clock and then circuits reformat the data using size information and address bits from the ASB bus. This allows byte, halfword and word accesses. Byte readback data are provided on all four byte lanes and halfword readback data are provided on both halfword lanes.
Subsystem Bridge Of Ambas Asb Bus To Peripheral Component Interconnect (Pci) Bus
Burton B. Lo - San Francisco CA Anthony L. Pan - Fremont CA
Assignee:
3COM Corporation - Santa Clara CA
International Classification:
G06F 1300
US Classification:
712 41, 712 38
Abstract:
A method and apparatus to bridge between the PCI bus and a RISC processor interface bus. In one embodiment, the present invention is a single-ASIC implementation rather than a design using multiple discrete circuit components. The invention incorporates a method and apparatus that will minimize subsystem latencies and inefficiencies in order to maximize data throughput and system performance. In yet another embodiment, the RISC processor interface bus is the AMBA ASB bus. The invention further provides an Advanced RISC Machine interface bus unit which uses an improved clock crossing handshake mechanism that can support a range of clock frequencies on the AMBA ASB bus.
System And Method To Reduce Electromagnetic Interference Emissions In A Network Interface
Marwan A. Fawal - Santa Clara CA Burton B. Lo - San Francisco CA Anthony L. Pan - Fremont CA George Kwan - Sunnyvale CA
Assignee:
3Com Corporation - Santa Clara CA
International Classification:
H04L 1266
US Classification:
370463
Abstract:
A system for reducing electromagnetic interference emissions is described. The system can include a network interface card with an Ethernet controller circuit. The Ethernet controller circuit generates an Ethernet output signal that includes a pre-emphasis component and a data component. The Ethernet controller circuit monitors the Ethernet output signal and adjusts the levels of the pre-emphasis component and the data component to reduce the electromagnetic interference caused by the network interface card but still fit the requirements for valid Ethernet signals.
Scaleable Priority Arbiter For Arbitrating Between Multiple Fifo Entry Points Of A Network Interface Card
Burton B. Lo - San Francisco CA Krishna Uppunda - Santa Clara CA Anthony L. Pan - Fremont CA
Assignee:
3Com Corporation - Santa Clara CA
International Classification:
H04L 1228
US Classification:
370412, 370428
Abstract:
A scaleable priority arbiter for arbitrating between multiple FIFO entry points of a network interface card (NIC). The circuit provides a separate FIFO entry point circuit within the NIC for each data packet priority type. Exemplary priority types, from highest to lowest, include isochronous, priority , priority ,. . . , priority n. A separate set of FIFO entry points are provided for NIC transmitting (Tx) and for NIC receiving (Rx). For each of the Tx FIFO entry points, a single Tx entry point register is seen by the processor and multiple downlist pointers are also maintained. The Tx entry point registers all feed a scaleable priority arbiter which selects the next message for transmission. The scaleable priority arbiter is made of scaleable circuit units that contain a sequential element controlling a multiplexer. The multiplexer selects between two inputs, a first input is dedicated to data packets of the priority type corresponding to the circuit stage and the other input comes from the lower priority chain.
George Kwan - Sunnyvale CA Maria B. Hu - San Jose CA Burton B. Lo - San Francisco CA Anthony Pan - Fremont CA
Assignee:
3Com Corporation - Santa Clara CA
International Classification:
H04M 1100
US Classification:
379 9315, 379 9305, 379 9306, 37938702, 37939201
Abstract:
An integrated circuit is provided to convert an analog telephone signal into a digital format. The integrated circuit includes an analog-digital converter coupled to an averager. Sampled analog values are averaged at intervals and compared to a threshold level to determine a digital value.
Current Controlled Oscillator With Voltage Independent Capacitance
Marwan A. Fawal - Santa Clara CA Burton B. Lo - San Francisco CA Ruchi Wadhawan - Sunnyvale CA
Assignee:
3Com Corporation - Santa Clara CA
International Classification:
H01G 9048 H03L 7085
US Classification:
331111
Abstract:
A current-controlled oscillator with first and second differential comparators (640, 840) serving as inputs, first and second voltage independent multi-layered integrated capacitors (600, 800) corresponding to the first and second comparators (640, 840), and a RS latch (700) for switching operation between the two comparators (640, 840) thereby achieving oscillation. The multi-layered integrated capacitors (600, 800) are designed to provide voltage independent capacitance.
Googleplus
Burton Lo
Tagline:
I am a technology consultant, project manager, photographer, counselor, coach, and father.