Berni W Landau
age ~67
from Beaverton, OR
- Also known as:
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- Berni Julie Landau
- Berni A Landau
- Bernd W Landau
- Walter Landau Berni
- Landau Berni
- Phone and address:
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16225 Nighthawk Dr, Beaverton, OR 97007
503-579-8172
Berni Landau Phones & Addresses
- 16225 Nighthawk Dr, Beaverton, OR 97007 • 503-579-8172
- Aloha, OR
- Portland, OR
- Puyallup, WA
- 16225 SW Nighthawk Dr, Beaverton, OR 97007 • 503-347-3823
Work
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Company:Intel corporationJun 2012
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Position:Manager of tape-in collateral
Education
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Degree:Masters
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School / High School:Stanford University
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Specialities:Materials Science
Industries
Semiconductors
Us Patents
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Photodiode Structure
view source -
US Patent:6372607, Apr 16, 2002
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Filed:Jun 30, 1999
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Appl. No.:09/343841
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Inventors:Berni W. Landau - Beaverton OR
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Assignee:Intel Corporation - Santa Clara CA
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International Classification:H01L 2176
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US Classification:438439, 438 48, 438 22, 438 45, 438414, 438449
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Abstract:A circuit that includes an isolation boundary formed to a depth in a substrate defining an active area of the substrate, a primary junction formed in the active area to a primary junction depth in the substrate to collect electron/hole pairs, and a secondary junction formed in the active area adjacent to the isolation boundary to a secondary junction depth at least equal to the isolation boundary depth.
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Reduced Leakage Trench Isolation
view source -
US Patent:6403394, Jun 11, 2002
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Filed:Mar 29, 2001
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Appl. No.:09/821561
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Inventors:Kevin M. Connolly - Chandler AZ
Jung S. Kang - Chandler AZ
Berni W. Landau - Beaverton OR
James E. Breisch - Chandler AZ
Akira Kakizawa - Phoenix AZ -
Assignee:Intel Corporation - Santa Clara CA
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International Classification:H01L 21329
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US Classification:438 57, 438 73
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Abstract:Leakage current may be reduced in trench isolated semiconductor devices by providing a buffer between the trench isolation and an active area For example, with a trench isolated photodiode, a buffer of opposite conductivity type may be provided between the trench and the diffusion that forms the p-n junction of the photodiode.
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Reduced Leakage Trench Isolation
view source -
US Patent:6410359, Jun 25, 2002
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Filed:Mar 26, 2001
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Appl. No.:09/817639
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Inventors:Kevin M. Connolly - Chandler AZ
Jung S. Kang - Chandler AZ
Berni W. Landau - Beaverton OR
James E. Breisch - Chandler AZ
Akira Kakizawa - Phoenix AZ
Mark A. Beiley - Chandler AZ
Cory E. Weber - Beaverton OR
Shaofeng Yu - Lake Oswego OR -
Assignee:Intel Corporation - Santa Clara CA
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International Classification:H01L 2100
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US Classification:438 48
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Abstract:Leakage current may be reduced in trench isolated semiconductor devices by providing a buffer between the trench isolation and an active area. For example, with a trench isolated photodiode, a buffer of opposite conductivity type may be provided between the trench and the diffusion that forms the p-n junction of the photodiode.
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Embedded Dielectric Film For Quantum Efficiency Enhancement In A Cmos Imaging Device
view source -
US Patent:61304220, Oct 10, 2000
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Filed:Jun 29, 1998
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Appl. No.:9/106738
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Inventors:Edward J. Bawolek - Chandler AZ
Robert C. Sundahl - Phoenix AZ
Berni W. Landau - Beaverton OR
Stephen B. Gospe - Fremont CA
Jack S. Uppal - San Jose CA
Jung S. Kang - Chandler AZ -
Assignee:Intel Corporation - Santa Clara CA
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International Classification:H01L 2700
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US Classification:2502081
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Abstract:The present invention is an image sensor and its fabricating method. The image sensor comprises a photodiode and a dielectric structure. The photodiode is responsive to an amount of incident light from a light source. The dielectric structure is on top of the photodiode and is placed between the photodiode and an inter-level dielectric (ILD) oxide layer. The dielectric structure contains a dielectric material. The ILD oxide layer is made of an oxide material and has an ILD oxide thickness.
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Reduced Leakage Trench Isolation
view source -
US Patent:62591452, Jul 10, 2001
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Filed:Jun 17, 1998
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Appl. No.:9/098881
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Inventors:Kevin M. Connolly - Chandler AZ
Jung S. Kang - Chandler AZ
Berni W. Landau - Beaverton OR
James E. Breisch - Chandler AZ
Akira Kakizawa - Phoenix AZ -
Assignee:Intel Corporation - Santa Clara CA
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International Classification:H01L 27146
H01L 3100 -
US Classification:257431
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Abstract:Leakage current may be reduced in trench isolated semiconductor devices by providing a buffer between the trench isolation and an active area. For example, with a trench isolated photodiode, a buffer of opposite conductivity type may be provided between the trench and the diffusion that forms the p-n junction of the photodiode.
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Reduced Leakage Trench Isolation
view source -
US Patent:62151657, Apr 10, 2001
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Filed:May 12, 1999
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Appl. No.:9/310423
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Inventors:Kevin M. Connolly - Chandler AZ
Jung S. Kang - Chandler AZ
Berni W. Landau - Beaverton OR
James E. Breisch - Chandler AZ
Akira Kakizawa - Phoenix AZ
Joseph W. Parks - Hillsboro OR
Mark A. Beiley - Chandler AZ
Cory E. Weber - Beaverton OR
Shaofeng Yu - Lake Oswego OR -
Assignee:Intel Corporation - Santa Clara CA
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International Classification:H01L 310232
H01L 3106
H01L 2100 -
US Classification:257437
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Abstract:Leakage current may be reduced in trench isolated semiconductor devices by providing a buffer between the trench isolation and an active area. For example, with a trench isolated photodiode, a buffer of opposite conductivity type may be provided between the trench and the diffusion that forms the p-n junction of the photodiode.
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Shallow Trench Isolation Technique
view source -
US Patent:57190852, Feb 17, 1998
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Filed:Sep 29, 1995
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Appl. No.:8/536694
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Inventors:Peter K. Moon - Portland OR
Berni W. Landau - Beaverton OR
David T. Krick - Hillsboro OR -
Assignee:Intel Corporation - Santa Clara CA
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International Classification:H01L 2176
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US Classification:438424
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Abstract:A method of forming a trench isolation region. The method of the present invention comprises the steps of forming an opening in a semiconductor substrate, oxidizing the opening a first time, and then etching the oxidized opening with a wet etchant comprising HF. The opening is then oxidized a second time.
Resumes
Berni Landau
view sourceLocation:
Hillsboro, OR
Industry:
Semiconductors
Work:
Intel Corporation
Manager of Tape-In Collateral
Intel Corporation
Ret Integration Engineer
Manager of Tape-In Collateral
Intel Corporation
Ret Integration Engineer
Education:
Stanford University
Masters, Materials Science
Masters, Materials Science
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