Aws Z Shallal

US Patent:

8494363, Jul 23, 2013

Filed:

Apr 21, 2011

Appl. No.:

13/091908

Inventors:

Juan-Carlos Calderon - Fremont CA, US
Jean-Michel Caia - Plymouth CA, US
Arun Zarabi - Sacramento CA, US
Aws Shallal - Cary NC, US
Theron Paul Niederer - Raleigh NC, US

Assignee:

Cortina Systems, Inc. - Sunnyvale CA

International Classification:

H04B 10/00

US Classification:

398 43, 398154, 370503, 370506

Abstract:

Signal format conversion apparatus and methods involve converting data signals between a first signal format associated with a first reference clock rate and a second signal format that is different from the first signal format and is associated with a second reference clock rate different from the first reference clock rate. A period of the second signal format is changed to match a period of a third signal format by controlling a synchronized second reference clock rate that is applied in converting data signals between the first signal format and the second signal format. The synchronized second reference clock rate is different from the second reference clock rate and is synchronized with a third reference clock rate. The third reference clock rate is associated with the third signal format. Such synchronization simplifies conversion of signals between the second and third signal formats.

US Patent:

8510626, Aug 13, 2013

Filed:

Dec 8, 2011

Appl. No.:

13/314970

Inventors:

Sebastian Ziesler - Boston MA, US
Aws Shallal - Durham NC, US

Assignee:

Cortina Systems, Inc. - Sunnyvale CA

International Classification:

H03M 13/00

US Classification:

714758, 702189

Abstract:

Data encoding apparatus and methods are disclosed. A Cyclic Redundancy Check (CRC) coding module is selected, from a plurality of different CRC coding modules, for coding a block of information. A generic coder, which is configurable to perform CRC coding based on any of the plurality of different CRC coding modules, is configured to perform CRC coding for the block of information based on the selected CRC coding module. A block of information for which a coding operation is to be performed may be segmented into a plurality of segments having respective lengths. Respective generic coders may be configured to perform the coding operation for the plurality of segments. In this case, a result of the coding operation for the block of information may be determined based on results of the coding operations for the plurality of data segments.

US Patent:

20080307288, Dec 11, 2008

Filed:

Jun 8, 2007

Appl. No.:

11/808409

Inventors:

Sebastian Ziesler - Boston MA, US
Aws Shallal - Durham NC, US

International Classification:

H03M 13/00

US Classification:

714758

Abstract:

Data encoding apparatus and methods are disclosed. A Cyclic Redundancy Check (CRC) coding module is selected, from a plurality of different CRC coding modules, for coding a block of information. A generic coder, which is configurable to perform CRC coding based on any of the plurality of different CRC coding modules, is configured to perform CRC coding for the block of information based on the selected CRC coding module. A block of information for which a coding operation is to be performed may be segmented into a plurality of segments having respective lengths. Respective generic coders may be configured to perform the coding operation for the plurality of segments. In this case, a result of the coding operation for the block of information may be determined based on results of the coding operations for the plurality of data segments.

US Patent:

20220358989, Nov 10, 2022

Filed:

Apr 20, 2022

Appl. No.:

17/725026

Inventors:

- San Jose CA, US
Aws Shallal - Cary NC, US
Joey M. Esteves - Tracy CA, US

International Classification:

G11C 11/4074

Abstract:

A power-management integrated circuit (PMIC) is installed on a memory module to optimize power use among a collection of memory devices. The PMIC includes external power-supply nodes that receive relatively high and low supply voltages. Depending on availability, the PMIC uses one or both of these supply voltages to generate a managed supply voltage for powering the memory devices. The PMIC selects between operational modes for improved efficiency in dependence upon the availability of one or both externally provided supply voltages.

US Patent:

20200356475, Nov 12, 2020

Filed:

Apr 23, 2020

Appl. No.:

16/856820

Inventors:

- Sunnyvale CA, US
Aws Shallal - Cary NC, US

International Classification:

G06F 12/0802
G06F 11/14
G06F 12/02

Abstract:

Disclosed herein are techniques for implementing hybrid memory modules with improved inter-memory data transmission paths. The claimed embodiments address the problem of implementing a hybrid memory module that exhibits improved transmission latencies and power consumption when transmitting data between DRAM devices and NVM devices (e.g., flash devices) during data backup and data restore operations. Some embodiments are directed to approaches for providing a direct data transmission path coupling a non-volatile memory controller and the DRAM devices to transmit data between the DRAM devices and the flash devices. In one or more embodiments, the DRAM devices can be port switched devices, with a first port coupled to the data buffers and a second port coupled to the direct data transmission path. Further, in one or more embodiments, such data buffers can be disabled when transmitting data between the DRAM devices and the flash devices.

US Patent:

20190286560, Sep 19, 2019

Filed:

Mar 25, 2019

Appl. No.:

16/363065

Inventors:

- Sunnyvale CA, US
Aws Shallal - Cary NC, US

International Classification:

G06F 12/0802
G06F 11/14

Abstract:

Disclosed herein are techniques for implementing hybrid memory modules with improved inter-memory data transmission paths. The claimed embodiments address the problem of implementing a hybrid memory module that exhibits improved transmission latencies and power consumption when transmitting data between DRAM devices and NVM devices (e.g., flash devices) during data backup and data restore operations. Some embodiments are directed to approaches for providing a direct data transmission path coupling a non-volatile memory controller and the DRAM devices to transmit data between the DRAM devices and the flash devices. In one or more embodiments, the DRAM devices can be port switched devices, with a first port coupled to the data buffers and a second port coupled to the direct data transmission path. Further, in one or more embodiments, such data buffers can be disabled when transmitting data between the DRAM devices and the flash devices.