Atul I Srinivasan

US Patent:

7092838, Aug 15, 2006

Filed:

Jun 4, 2004

Appl. No.:

10/860812

Inventors:

Prasanna Venkat Srinivas - Cupertino CA, US
Atul Srinivasan - Santa Clara CA, US
Shankar Krishnamoorthy - Saratoga CA, US

Assignee:

Sierra Design Automation, Inc. - Santa Clara CA

International Classification:

H01L 23/48

US Classification:

702117

Abstract:

A method and apparatus are presented that can analyze the performance of an integrated circuit design at multiple corners, under multiple modes, and for multiple objectives efficiently and simultaneously. The extraction, timing analysis, and optimization functions are integrated into a mechanism that provides a novel problem formulation. A plurality of virtual timing graphs are maintained and updated simultaneously by providing a data structure that can efficiently store operating data for an arbitrary number of conditions at each node. This data structure is populated according to the design, and as optimizations are made, the operating data for all design conditions is updated simultaneously. Timing violations can be reported across all corners and modes. By integrating this multi-corner multi-mode analysis with circuit optimization, a convergent mechanism is provided.