Ara R Aslyan

US Patent:

20110185323, Jul 28, 2011

Filed:

Aug 23, 2010

Appl. No.:

12/861824

Inventors:

WILLIAM MATTHEW HOGAN - LAKE OSWEGO OR, US
DUSAN PETRANOVIC - CUPERTINO CA, US
ARA ASLYAN - MOUNTAIN VIEW CA, US

International Classification:

G06F 17/50

US Classification:

716 52

Abstract:

Techniques for performing physical verification processes for stacked integrated circuit devices. An interface between a first two-dimensional integrated circuit device and a second two-dimensional integrated circuit device is identified. The design data for the identified layers in the first and second two-dimensional integrated circuit devices are then combined and physically verified as a single set of interface design data. The design data for the first two-dimensional integrated circuit device and the second two-dimensional integrated circuit device are then separately physically verified. Once the interface design data, the first two-dimensional integrated circuit device design data and the second two-dimensional integrated circuit device design data have been physically verified, the verified design can be recombined to form verified design data corresponding to a stacked integrated circuit device.