Antonio F Valles

US Patent:

20040123280, Jun 24, 2004

Filed:

Dec 19, 2002

Appl. No.:

10/325169

Inventors:

Gautam Doshi - Santa Clara CA, US
Dattatraya Kulkarni - Santa Clara CA, US
Anthony Roide - Phoenix AZ, US
Antonio Valles - Gilbert AZ, US

International Classification:

G06F009/45

US Classification:

717/161000, 717/150000

Abstract:

An embodiment of a compiler technique for decreasing sparse matrix computation runtime parallelizes loads from adjacent iterations of unrolled loop code. A dependence check code is statically inserted to identify dependence between store and load dynamically, and information is passed to a code scheduler for scheduling independent parallel computation and potentially dependent computations at suitable latencies.

US Patent:

20170177346, Jun 22, 2017

Filed:

Dec 20, 2015

Appl. No.:

14/975809

Inventors:

- Santa Clara CA, US
Charles R. Yount - Phoenix AZ, US
Antonio C. Valles - Gilbert AZ, US

International Classification:

G06F 9/30
G06F 12/08
G06F 9/38

Abstract:

A processor includes an execution unit to execute instructions to load indices from an array of indices, optionally perform scatters, and prefetch (to a specified cache) contents of target locations for future scatters from arbitrary locations in memory. The execution unit includes logic to load, for each target location of a scatter or prefetch operation, an index value to be used in computing the address in memory for the operation. The index value may be retrieved from an array of indices identified for the instruction. The execution unit includes logic to compute the addresses based on the sum of a base address specified for the instruction, the index value retrieved for the location, and a prefetch offset (for prefetch operations), with optional scaling. The execution unit includes logic to retrieve data elements from contiguous locations in a source vector register specified for the instruction to be scattered to the memory.

US Patent:

20170177349, Jun 22, 2017

Filed:

Dec 21, 2015

Appl. No.:

14/977356

Inventors:

- Santa Clara CA, US
Antonio C. Valles - Gilbert AZ, US
Indraneil M. Gokhale - Chandler AZ, US

International Classification:

G06F 9/30
G06F 15/80
G06F 9/38

Abstract:

A processor includes an execution unit to execute instructions to load indices from an array of indices, optionally perform a gather, and prefetch (to a specified cache) elements for a future gather from arbitrary locations in memory. The execution unit includes logic to load, for each element to be gathered or prefetched, an index value to be used in computing the address in memory for the element. The index value may be retrieved from an array of indices that is identified for the instruction. The execution unit includes logic to compute the address based on the sum of a base address that is specified for the instruction and the index value that was retrieved for the data element, with or without scaling. The execution unit includes logic to store gathered data elements in contiguous locations in a destination vector register that is specified for the instruction.

US Patent:

20170177360, Jun 22, 2017

Filed:

Dec 21, 2015

Appl. No.:

14/977445

Inventors:

- Santa Clara CA, US
Charles R. Yount - Phoenix AZ, US
Antonio C. Valles - Gilbert AZ, US

International Classification:

G06F 9/30
G06F 12/08

Abstract:

A processor includes an execution unit to execute instructions to load indices from an array of indices and scatter elements to locations in sparse memory based on those indices. The execution unit includes logic to load, for each data element to be scattered by the instruction, as needed, an index value to be used in computing the address in memory at which a particular data element is to be written. The index values may be retrieved from an array of indices identified for the instruction. The execution unit includes logic to compute the addresses based on the sum of a base address specified for the instruction and the index values retrieved for the data element locations, with optional scaling. The execution unit includes logic to retrieve data elements from contiguous locations in a source vector register specified for the instruction and store them to the computed locations.

US Patent:

20170177363, Jun 22, 2017

Filed:

Dec 22, 2015

Appl. No.:

14/979231

Inventors:

- Santa Clara CA, US
Indraneil M. Gokhale - Chandler AZ, US
Antonio C. Valles - Gilbert AZ, US

International Classification:

G06F 9/30
G06F 12/08

Abstract:

A processor includes an execution unit to execute instructions to load indices from an array of indices and gather elements from random locations or locations in sparse memory based on those indices. The execution unit includes logic to load, for each data element to be gathered by the instruction, as needed, an index value to be used in computing the address in memory of a particular data element to be gathered. The index value may be retrieved from an array of indices that is identified for the instruction. The execution unit includes logic to compute the address as the sum of a base address that is specified for the instruction and the index value that was retrieved for the data element, with or without scaling. The execution unit includes logic to store the gathered data elements in contiguous locations in a destination vector register that is specified for the instruction.

US Patent:

20160092681, Mar 31, 2016

Filed:

Sep 26, 2014

Appl. No.:

14/497523

Inventors:

Antonio C. Valles - Gilbert AZ, US
Vincent J. Zimmer - Federal Way WA, US

International Classification:

G06F 21/55
G06N 5/04

Abstract:

Systems and methods may provide for identifying a runtime behavioral pattern of an application and detecting an anomaly in the runtime behavioral pattern. In addition, a security event may be triggered in response to the anomaly. In one example, the anomaly is detected with regard to one or more of a library call count, a library call type, a library call argument configuration or a library call timing associated with a runtime operation of the application.