Anand Haridass

US Patent:

6930507, Aug 16, 2005

Filed:

Jul 10, 2003

Appl. No.:

10/616845

Inventors:

Daniel M. Dreps - Georgetown TX, US
Frank D. Ferraiolo - New Windsor NY, US
Anand Haridass - Austin TX, US
Bao Gia-Harvey Truong - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K019/003

US Classification:

326 30, 326 21, 326 86, 326 83, 327108, 710100

Abstract:

A termination network has multiple resistors forming multiple voltage dividers with a common node. Half of the resistors are coupled to the positive power supply voltage with P channel field effect transistors (PFETs) and the other half are coupled to the negative or ground power supply voltage with N channel FETs (NFETs). Logic signals are used to control the gates of the FETs. By modifying which FETs are ON, the termination network can be selectively controlled to produce various offset levels with the same impedance level. The impedance levels may also be modified while maintaining the same offset level. A delay circuit may be selectively employed to feedback control signals after a selected delay time to adjust the threshold level to dynamically or statically optimize signal reception.

US Patent:

6951002, Sep 27, 2005

Filed:

Jun 5, 2003

Appl. No.:

10/455164

Inventors:

Joachim Gerhard Clabes - Austin TX, US
Anand Haridass - Austin TX, US
Michael F. Wang - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F017/50

US Classification:

716 5, 716 7, 716 8

Abstract:

An improved method and system for integrated circuit device physical design and layout. The physical layout of the integrated circuit device is optimally stored in a database to provide improved analysis capabilities of the integrated circuit device's characteristics. The method and system evaluates local interactions between functional blocks and decoupling cells on a given floor plan of a chip using this optimized database in order to reduce memory and processor utilization. Local noise is projected by using dI/dt and capacitance estimates. Areas of highest noise concern are identified, and floor plan mitigation actions are taken by tuning the placement of neighboring decoupling cells and their properties. Upon several iterative cycles, a near optimal solution for a given floor plan of the total chip is achieved.

US Patent:

7208972, Apr 24, 2007

Filed:

May 13, 2004

Appl. No.:

10/845568

Inventors:

Daniel M. Dreps - Georgetown TX, US
Anand Haridass - Austin TX, US
Bao G. Truong - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 17/16

US Classification:

326 26, 326 30, 326 82

Abstract:

Two or more integrated circuit (IC) chips are separated by a significant distance relative to their communication frequency such that pseudo-differential signaling is used to improve signal detection. A derived reference voltage is generated that tracks the variations of the driver and receiver side power supply variations that normally reduce noise margins. The derived reference voltage is filtered to reduce high frequency response and coupled as the reference to differential receivers used to detect the logic levels of the communication signals.

US Patent:

7233170, Jun 19, 2007

Filed:

Aug 25, 2005

Appl. No.:

11/211955

Inventors:

Wiren Dale Becker - Hyde Park NY, US
Anand Haridass - Austin TX, US
Bao G. Truong - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 19/00

US Classification:

326 93, 327158, 327161

Abstract:

Data busses are configured as N differential channels driven by a data signal and its complement through two off-chip drivers (OCDs). Each OCD is preceded by a programmable delay element and a two way MUX. The two data channels either transmit the data signals or a common clock signal as determined by a select signal from a skew controller. The differential signals are received in a differential receiver and a phase detector. The output of the phase detector in each differential channel is routed through an N×1 MUX. The N×1 MUX is controlled by the skew controller. The output of the N×1 MUX is fed back as a phase error feedback signal to the skew controller. Each differential data channel is sequentially selected and the programmable delays are adjusted until the phase error feedback signal from the selected phase detector reaches a predetermined minimum allowable value. Periodic adjustment may be implemented for calibration.

US Patent:

7239213, Jul 3, 2007

Filed:

Aug 23, 2005

Appl. No.:

11/209549

Inventors:

Daniel M. Dreps - Georgetown TX, US
Anand Haridass - Austin TX, US
Bao G. Truong - Austin TX, US
Joel D. Ziegelbein - Iowa City IA, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01P 1/00

US Classification:

333 1, 333 5, 326 30, 326 86

Abstract:

Signaling between two or more ICs use a signaling scheme wherein a reference signal is generated at the driver side and the receiver side. The driver side reference signal is coupled to the receiver side reference signal with a transmission line channel forming a reference channel. Data signal channels are paired with a reference channel between each two adjacent data channels. Adjacent pairs of data signal channels are each separated with an empty wiring channel. The paired data signals are received in one input of a differential receiver. The reference signal of the reference channel between the two paired data channels is coupled to the other input of the two differential receivers. Coupling from the paired data channels to the reference channel appears a common mode noise and is rejected by the differential receivers. The number of channels is reduced from a full differential signaling scheme.

US Patent:

7266788, Sep 4, 2007

Filed:

Jul 19, 2005

Appl. No.:

11/184350

Inventors:

Anand Haridass - Austin TX, US
Andreas Huber - Austin TX, US
Erich Klink - Schoenaich, DE
Thomas Strach - Wildberg, DE
Jochen Supper - Herrenberg, DE

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50

US Classification:

716 1, 716 8

Abstract:

A carrier for an electronic device such as an integrated circuit chip is designed by assigning two different voltage domains to two separate areas of the contact surface of the carrier, while providing a common electrical ground for both voltage domains. The integrated circuit chip may be a microprocessor having a nominal operating voltage, and the different voltages of the two voltage domains are both within the tolerance range of the nominal operating voltage but one of the voltage domains is aligned with a high power density area of the microprocessor (e. g. , the microprocessor core) and provides a slightly greater voltage. The higher power voltage domain preferably has a ratio of voltage pins to ground pins that is greater than one.

US Patent:

7302664, Nov 27, 2007

Filed:

Feb 10, 2005

Appl. No.:

11/054916

Inventors:

Anand Haridass - Austin TX, US
Andreas Huber - Austin TX, US
Erich Klink - Schoenaich, DE
Jochen Supper - Herrenberg, DE

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50

US Classification:

716 10, 716 5

Abstract:

A system and method for automatic insertion of on-chip decoupling capacitors are provided. With the system and method, an integrated circuit design is partitioned into cells and the noise distribution per cell of an integrated circuit is determined. This noise distribution may be generated using any of a number of different known mechanisms and generally results in a noise-map being generated for the integrated circuit. Thereafter, a mapping function is applied to the noise map for each cell to determine a required capacitance for the cells of the integrated circuit. From this required capacitance per cell, the necessary decoupling capacitors may be identified as well as the location for insertion of these decoupling capacitors. In a similar manner, decoupling capacitors may be removed from cells of the integrated circuit based upon the determined required capacitance per cell.

US Patent:

7348667, Mar 25, 2008

Filed:

Mar 22, 2005

Appl. No.:

11/086719

Inventors:

Sungjun Chun - Austin TX, US
Jason Lee Frankel - Wappingers Falls NY, US
Anand Haridass - Austin TX, US
Erich Klink - Schoenaich, DE
Brian Leslie Singletary - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 23/34

US Classification:

257723, 257686

Abstract:

A system and method for reducing noise in a multi-layer ceramic package are provided. With the system and method, additional shielding wires are inserted into the reference planes wherever there are no signal vias present. These additional lines in the reference planes force stronger signal interaction with the reference (vdd/gnd) thereby reducing the interaction between the signals in the signal layers. As a result, the noise present in the signals of the signal layers is reduced.