Alper Meryem Halbutogullari

US Patent:

7376927, May 20, 2008

Filed:

Jun 13, 2005

Appl. No.:

11/151045

Inventors:

Alper Halbutogullari - Santa Clara CA, US
Timur Ceylan - Santa Clara CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 17/50

US Classification:

716 12, 716 2, 716 10, 716 13, 716 14

Abstract:

For routing points to a center point, the points are grouped into a respective set disposed within each quadrant. Each point is Manhattan routed to any other point having a minimum Manhattan distance within a rectangle defined by each point and the center point, to result in at least one initial end point in each quadrant having at least one of the points. The at least one initial end point is Manhattan routed together to result in a respective final end point in each quadrant having at least one of the points. The respective final end points are routed to the center point with minimized routing distance.

US Patent:

7188325, Mar 6, 2007

Filed:

Oct 4, 2004

Appl. No.:

10/957848

Inventors:

Marius Evers - Sunnyvale CA, US
Jeffrey E. Trull - San Jose CA, US
Alper Halbutogullari - Santa Clara CA, US
Robert W. Williams - San Jose CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 17/50

US Classification:

716 4, 716 2

Abstract:

In one embodiment, a method for selecting transistor threshold voltages on an integrated circuit may include assigning a first threshold voltage to selected groups of transistors such as cell instances, for example, and determining which of the selected groups of transistors to assign a second threshold voltage, that is lower than the first threshold voltage, by iteratively performing a cost/benefit analysis. The method may further include determining which of the selected groups of transistors having a third threshold voltage to assign the first threshold voltage by iteratively performing a cost/benefit analysis. The cost/benefit analysis may include calculating a cost/benefit ratio for each group of the selected groups of transistors. In addition, the cost/benefit analysis may include calculating an upcone benefit and a downcone benefit for groups of transistors coupled to one or more inputs and outputs, respectively.