Alexander L Mak

US Patent:

6847553, Jan 25, 2005

Filed:

Feb 3, 2003

Appl. No.:

10/357840

Inventors:

Jian Chen - San Jose CA, US
Long C. Pham - San Jose CA, US
Alexander K. Mak - Los Altos CA, US

Assignee:

SanDisk Corporation - Sunnyvale CA

International Classification:

G11C 1600

US Classification:

36518509, 36518503

Abstract:

Techniques of overcoming a degradation of the apparent charge levels stored in one row of memory cells as a result of subsequently programming an adjacent row of memory cells. After storing the data of the subsequently programmed row elsewhere, the charge levels of its cells are driven to common level. The charge levels of the first row of cells then have a uniform influence from the charge levels of the second row, and, as a result, the chance of successfully reading the data stored in the first row is significantly increased.

US Patent:

6944068, Sep 13, 2005

Filed:

Mar 24, 2004

Appl. No.:

10/809571

Inventors:

Khandker N. Quader - Sunnyvale CA, US
Khanh T. Nguyen - Sunnyvale CA, US
Feng Pan - San Jose CA, US
Long C. Pham - San Jose CA, US
Alexander K. Mak - Los Altos Hills CA, US

Assignee:

SanDisk Corporation - Sunnyvale CA

International Classification:

G11C016/06

US Classification:

36518922, 36518503, 36518512, 36518524

Abstract:

A multi-level non-volatile memory cell programming/lockout method and system are provided. The programming/lockout method and system advantageously prevent memory cells that charge faster than other memory cells from being over-programmed.

US Patent:

6967872, Nov 22, 2005

Filed:

Dec 18, 2001

Appl. No.:

10/025749

Inventors:

Khandker N. Quader - Sunnyvale CA, US
Khanh T. Nguyen - Sunnyvale CA, US
Feng Pan - San Jose CA, US
Long C. Pham - San Jose CA, US
Alexander K. Mak - Los Altos Hills CA, US

Assignee:

SanDisk Corporation - Sunnyvale CA

International Classification:

G11C016/04

US Classification:

36518522, 36518502, 36518503

Abstract:

A multi-level non-volatile memory cell programming/lockout method and system are provided. The programming/lockout method and system advantageously prevent memory cells that charge faster than other memory cells from being over-programmed.

US Patent:

7095654, Aug 22, 2006

Filed:

Sep 9, 2005

Appl. No.:

11/223709

Inventors:

Khandker N. Quader - Santa Clara CA, US
Khanh T. Nguyen - Sunnyvale CA, US
Feng Pan - San Jose CA, US
Long C. Pham - San Jose CA, US
Alexander K. Mak - Los Altos Hills CA, US

Assignee:

SanDisk Corporation - Milpitas CA

International Classification:

G11C 11/34

US Classification:

36518519, 36518518, 365196

Abstract:

A multi-level non-volatile memory cell programming/lockout method and system are provided. The programming/lockout method and system advantageously prevent memory cells that charge faster than other memory cells from being over-programmed.

US Patent:

7102924, Sep 5, 2006

Filed:

Jan 3, 2005

Appl. No.:

11/028906

Inventors:

Jian Chen - San Jose CA, US
Long C. Pham - San Jose CA, US
Alexander K. Mak - Los Altos CA, US

Assignee:

SanDisk Corporation - Milpitas CA

International Classification:

G11C 16/34

US Classification:

36518509, 36518502, 365200

Abstract:

Techniques of overcoming a degradation of the apparent charge levels stored in one row of memory cells as a result of subsequently programming an adjacent row of memory cells. After storing the data of the subsequently programmed row elsewhere, the charge levels of its cells are driven to common level. The charge levels of the first row of cells then have a uniform influence from the charge levels of the second row, and, as a result, the chance of successfully reading the data stored in the first row is significantly increased.

US Patent:

7110298, Sep 19, 2006

Filed:

Jul 20, 2004

Appl. No.:

10/896096

Inventors:

Farookh Moogat - Fremont CA, US
Yan Li - Milpitas CA, US
Alexander K. Mak - Los Altos CA, US

Assignee:

SanDisk Corporation - Sunnyvale CA

International Classification:

G11C 16/04

US Classification:

36518518, 36518519, 3651852

Abstract:

In a non-volatile memory system, when it is discovered that the voltage pump pulse provided by a charge pump for programming the memory cells does not match a reference voltage, the programming time period of the voltage pump pulse is adjusted to a value that remains substantially unchanged until the end of the programming cycle. In this manner, the fluctuation in the effective programming time period of the programming pulses is prevented for the remainder of the programming cycle so that a broadening of the threshold voltage distribution will not occur or will be reduced. This feature allows a short programming time period to be designated for the programming pulses for enhanced performance, while allowing the flexibility of increased program time period when the charge pump is operating under conditions that causes it to be slow and/or weak.

US Patent:

8102705, Jan 24, 2012

Filed:

Dec 10, 2009

Appl. No.:

12/635449

Inventors:

Bo Liu - Milpitas CA, US
Yan Li - Milpitas CA, US
Alexander Kwok-Tung Mak - Los Altos Hills CA, US
Chi-Ming Wang - Fremont CA, US
Eugene Jinglun Tam - Saratoga CA, US
Kwang-ho Kim - Pleasanton CA, US

Assignee:

SanDisk Technologies Inc. - Plano TX

International Classification:

G11C 16/04
G11C 7/10

US Classification:

36518503, 36518917, 36518905, 36518518, 714773, 714E11032

Abstract:

Techniques for the reading and writing of data in multi-state non-volatile memories are described. Data is written into the memory in a binary format, read into the data registers on the memory, and “folded” within the registers, and then written back into the memory in a multi-state format. In the folding operation, binary data from a single word line is folded into a multi-state format and, when rewritten in multi-state form, is written into a only a portion of another word line. A corresponding reading technique, where the data is “unfolded” is also described. The techniques further allow for the data to be encoded with an error correction code (ECC) on the controller that takes into account its eventual multi-state storage prior to transferring the data to the memory to be written in binary form. A register structure allowing such a “folding” operation is also presented. One set of embodiments include a local internal data bus that allows data to between the registers of different read/write stacks, where the internal bus can used in the internal data folding process.

US Patent:

8132045, Mar 6, 2012

Filed:

Jun 16, 2009

Appl. No.:

12/485827

Inventors:

Chris Nga Yee Avila - Sunnyvale CA, US
Jonathan Hsu - Newark CA, US
Alexander Kwok-Tung Mak - Los Altos Hills CA, US
Jian Chen - Menlo Park CA, US
Grishma Shailesh Shah - San Jose CA, US

Assignee:

SanDisk Technologies, Inc. - Plano TX

International Classification:

G06F 11/00

US Classification:

714 621, 711103, 711118, 714 51, 714 61, 714 611, 714 62, 714 42

Abstract:

In a nonvolatile memory system, data received from a host by a memory controller is transferred to an on-chip cache, and new data from the host displaces the previous data before it is written to the nonvolatile memory array. A safe copy is maintained in on-chip cache so that if a program failure occurs, the data can be recovered and written to an alternative location in the nonvolatile memory array.