Alban D Douillet

US Patent:

20130304996, Nov 14, 2013

Filed:

Dec 27, 2012

Appl. No.:

13/728990

Inventors:

Jaydeep Marathe - San Jose CA, US
Manjunath Kudlur - San Jose CA, US
Vinod Grover - Mercer Island WA, US
Geoffrey Gerfin - Sunnyvale CA, US
Alban Douillet - Cupertino CA, US
Mayank Kaushik - Santa Clara CA, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

G06F 3/06

US Classification:

711150

Abstract:

A system and method for detecting shared memory hazards are disclosed. The method includes, for a unit of hardware operating on a block of threads, mapping a plurality of shared memory locations assigned to the unit to a tracking table. The tracking table comprises an initialization bit as well as access type information, collectively called the state tracking bits for each shared memory location. The method also includes, for an instruction of a program within a barrier region, identifying a second access to a location in shared memory within a block of threads executed by the hardware unit. The second access is identified based on a status of the state tracking bits. The method also includes determining a hazard based on a first type of access and a second type of access to the shared memory location. Information related to the first access is provided in the table.

US Patent:

20150206277, Jul 23, 2015

Filed:

Jan 20, 2015

Appl. No.:

14/601223

Inventors:

- Santa Clara CA, US
Ashish SRIVASTAVA - Bangalore, IN
Yogesh KINI - Bangalore, IN
Alban DOUILLET - San Jose CA, US
Geoffrey GERFIN - San Jose CA, US
Mayank KAUSHIK - Santa Clara CA, US
Nikita SHULGA - Cupertino CA, US
Vyas VENKATARAMAN - Braintree MA, US
David FONTAINE - Mountain View CA, US
Mark HAIRGROVE - San Jose CA, US
Piotr JAROSZYNSKI - Sunnyvale CA, US
Stephen JONES - San Francisco CA, US
Vivek KINI - Sunnyvale CA, US

International Classification:

G06T 1/60
G06F 12/10
G06T 1/20

Abstract:

The present invention facilitates efficient and effective utilization of unified virtual addresses across multiple components. In one embodiment, the presented new approach or solution uses Operating System (OS) allocation on the central processing unit (CPU) combined with graphics processing unit (GPU) driver mappings to provide a unified virtual address (VA) across both GPU and CPU. The new approach helps ensure that a GPU VA pointer does not collide with a CPU pointer provided by OS CPU allocation (e.g., like one returned by “malloc” C runtime API, etc.).

US Patent:

20140189647, Jul 3, 2014

Filed:

Dec 31, 2012

Appl. No.:

13/732282

Inventors:

- Santa Clara CA, US
Alban Douillet - Cupertino CA, US
Geoffrey Gerfin - Sunnyvale CA, US
Vyas Venkataraman - Santa Clara CA, US
Mark Hairgrove - San Jose CA, US
Riley Andrews - Palo Alto CA, US

Assignee:

NVIDIA CORPORATION - Santa Clara CA

International Classification:

G06F 11/36

US Classification:

717124

Abstract:

A system and method for debugging an executing program. The method includes executing a general-purpose computing on graphics processing units (GPGPU) program. The GPGPU program comprises a first portion operable to execute on a central processing unit (CPU) and a second portion operable to execute on a graphics processing unit (GPU). The method further includes attaching a debugging program to the first portion of the GPGPU program and modifying the first portion of the GPGPU program. The attaching of the debugging program to the first portion of the GPGPU program pauses execution of the first portion of the GPGPU program. The method further includes resuming execution of the first portion of the GPGPU program and accessing a first state information corresponding to the first portion of the GPGPU program. Execution of the first portion of the GPGPU program may then be paused. The first state information may then be used to access a second state information corresponding to the second portion of the GPGPU program.