Ajay K Ravi

US Patent:

7926019, Apr 12, 2011

Filed:

Feb 29, 2008

Appl. No.:

12/039918

Inventors:

Ajay K. Ravi - San Jose CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

G06F 9/455
G06F 17/50

US Classification:

716134, 716108

Abstract:

Method, computer program and system to perform timing analysis of designs containing clock networks by eliminating Common Clock Path Pessimism. The method includes transforming a clock network into a clock tree that includes nodes with different clock signal arrival times and leaf nodes representing source and destination registers. The tree is populated with information regarding the source and destination registers and the associated timing for the clock arrival signal. The method then enumerates Common Clock Path Pessimism (CCPP) groups, where any source register and any destination register in a CCPP group have the same nearest common ancestor node in the clock tree. The creation of CCPP groups enables analysis time reduction because only one timing calculation is required for the CCPP group instead of having to perform the analysis for each possible pair of registers. The method eliminates CCPP for each CCPP group and then displays the results.

US Patent:

8028260, Sep 27, 2011

Filed:

Oct 14, 2008

Appl. No.:

12/251002

Inventors:

Ajay K. Ravi - San Jose CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

G06F 17/50

US Classification:

716113, 716100

Abstract:

Methods and computer programs for determining the top most critical timing paths in an integrated circuit (IC) based on a timing graph of registers and combinational nodes in the IC are provided. One method generates the most critical path to each destination register and invokes a function to calculate the next critical path in each destination register a number of times according to the number of top most critical paths desired. The method uses recursion to calculate critical paths on the different nodes by recursively calling a function to calculate the next critical path on a fan-in node, where the fan-in node corresponds to the node which last contributed a critical path. Further, the most critical path to the node is selected in the recursive function. The critical paths are used to determine if the IC is stable under the analyzed clock frequency.

US Patent:

8205178, Jun 19, 2012

Filed:

Apr 11, 2011

Appl. No.:

13/084209

Inventors:

Ajay K. Ravi - San Jose CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

G06F 17/50
G06F 9/455

US Classification:

716108, 716104, 716134

Abstract:

Method, computer program and system to perform timing analysis of designs containing clock networks by eliminating Common Clock Path Pessimism. The method includes transforming a clock network into a clock tree that includes nodes with different clock signal arrival times and leaf nodes representing source and destination registers. The tree is populated with information regarding the source and destination registers and the associated timing for the clock arrival signal. The method then enumerates Common Clock Path Pessimism (CCPP) groups, where any source register and any destination register in a CCPP group have the same nearest common ancestor node in the clock tree. The creation of CCPP groups enables analysis time reduction because only one timing calculation is required for the CCPP group instead of having to perform the analysis for each possible pair of registers. The method eliminates CCPP for each CCPP group and then displays the results.

US Patent:

8519763, Aug 27, 2013

Filed:

Jun 11, 2010

Appl. No.:

12/814344

Inventors:

Ajay K. Ravi - San Jose CA, US
David Lewis - Toronto, CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K 3/017

US Classification:

327175, 327291

Abstract:

Integrated circuits that support dual-edge clocking are provided. Integrated circuits may include phase-locked loops that generate square-wave clock signals. The clock signals may be provided from off-chip equipment through input-output pins. The clock signals may be routed through a clock distribution network to provide local clock signals to pulse generators that generate clock pulses on rising and falling clock edges. The pulse generators may generate clock pulses that are triggered by the rising and falling clock edges with a common pulse width for optimum performance. Duty cycle distortion introduced by the clock network may be minimized for optimum performance. Adaptive duty cycle distortion circuitry may be used to control the pull-up/pull-down drive strengths of the clock buffer so that the high clock phase of the local clock signals is approximately a half clock cycle.

US Patent:

7424692, Sep 9, 2008

Filed:

Apr 12, 2006

Appl. No.:

11/279552

Inventors:

Ajay K Ravi - San Jose CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

G06F 9/45
G06F 17/50

US Classification:

716 6

Abstract:

A method is provided for determining a worst-case single cycle setup time between a first and second clock domain. First, an offset time of a second clock domain with respect to a first clock domain is normalized. A base period of the first clock domain and the second clock domain is then obtained. Next, a first greatest common denominator (GCD) shared by the first and second clock domains and the normalized second clock domain offset time is factored. Then, a reduced offset time and a reduced offset time size factor are substituted into an expression representing a relationship between the first and second clock domains. A second GCD shared by the first and second clock domains is factored from the expression and a modulus value of the reduced offset time and the second GCD is computed. Based on the modulus value, the worst-case single cycle setup time is computed.