Adolfo M Nemirovsky

US Patent:

6389449, May 14, 2002

Filed:

Mar 22, 1999

Appl. No.:

09/273810

Inventors:

Mario D. Nemirovsky - Saratoga CA
Adolfo M. Nemirovsky - San Jose CA
Narendra Sankar - Santa Clara CA

Assignee:

Clearwater Networks, Inc. - Los Gatos CA

International Classification:

G06F 900

US Classification:

709108, 712228

Abstract:

A multi-streaming processor has a plurality of streams for streaming one or more instruction threads, a set of functional resources for processing instructions from streams; and interstream control mechanisms whereby any stream may effect the operation of any other stream. In various embodiments the interstream control mechanisms include mechanisms for accomplishing one or more of enabling or disabling another stream, putting another stream into a sleep mode or awakening another stream from a sleep mode, setting priorities for another stream relative to access to functional resources, and granting blocking access by another stream to functional resources. A Master Mode is taught, wherein one stream is granted master status, and thereby may exert any and all available control mechanisms relative to other streams without interference by any stream. Supervisory modes are taught as well, wherein control may be granted from minimal to full control, with compliance of controlled streams, which may alter or withdraw control privileges. Various mechanisms are disclosed, including a mechanism wherein master status and interstream control hierarchy is recorded and amended by at least one on-chip bit map.

US Patent:

6477562, Nov 5, 2002

Filed:

Dec 16, 1998

Appl. No.:

09/216017

Inventors:

Mario D. Nemirovsky - Saratoga CA
Adolfo M. Nemirovsky - San Jose CA
Narendra Sankar - Santa Clara CA

Assignee:

Clearwater Networks, Inc. - Los Gatos CA

International Classification:

G06F 900

US Classification:

709108, 712 23

Abstract:

A multi-streaming processor has multiple streams for processing multiple threads, and an instruction scheduler including a priority record of priority codes for one or more of the streams. The priority codes determine in some embodiments relative access to resources as well as which stream has access at any point in time. In other embodiments priorities are determined dynamically and altered on-the-fly, which may be done by various criteria, such as on-chip processing statistics, by executing one or more priority algorithms, by input from off-chip, according to stream loading, or by combinations of these and other methods. In one embodiment a special code is used for disabling a stream, and streams may be enabled and disabled dynamically by various methods, such as by on-chip events, processing statistics, inpu from off-chip, and by processor interrupts. Some specific applications are taught, including for IP-routers and digital signal processors.

US Patent:

6789100, Sep 7, 2004

Filed:

Feb 8, 2002

Appl. No.:

10/071547

Inventors:

Mario D. Nemirovsky - Saratoga CA
Adolfo M. Nemirovsky - San Jose CA
Narendra Sankar - Santa Clara CA

Assignee:

MIPS Technologies, Inc. - Mountain View CA

International Classification:

G06J 900

US Classification:

709107, 713 1, 712 23

Abstract:

A multi-streaming processor has a plurality of streams for streaming one or more instruction threads, a set of functional resources for processing instructions from streams; and interstream control mechanisms whereby any stream may effect the operation of any other stream. In various embodiments the interstream control mechanisms include mechanisms for accomplishing one or more of enabling or disabling another stream, putting another stream into a sleep mode or awakening another stream from a sleep mode, setting priorities for another stream relative to access to functional resources, and granting blocking access by another stream to functional resources. A Master Mode is taught, wherein one stream is granted master status, and thereby may exert any and all available control mechanisms relative to other streams without interference by any stream. Supervisory modes are taught as well, wherein control may be granted from minimal to full control, with compliance of controlled streams, which may alter or withdraw control privileges. Various mechanisms are disclosed, including a mechanism wherein master status and interstream control hierarchy is recorded and amended by at least one on-chip bit map.

US Patent:

7020879, Mar 28, 2006

Filed:

May 14, 1999

Appl. No.:

09/312302

Inventors:

Mario D. Nemirovsky - Saratoga CA, US
Adolfo M. Nemirovsky - San Jose CA, US
Narendra Sankar - Santa Clara CA, US

Assignee:

MIPS Technologies, Inc. - Mountain View CA

International Classification:

G06F 9/46
G06F 15/76

US Classification:

718107, 712 23

Abstract:

A multi-streaming processor has a plurality of streams for streaming one or more instruction threads, a set of functional resources for processing instructions from streams, and interrupt handler logic. The logic detects and maps interrupts and exceptions to one or more specific streams. In some embodiments one interrupt or exception may be mapped to two or more streams, and in others two or more interrupts or exceptions may be mapped to one stream. Mapping may be static and determined at processor design, programmable, with data stored and amendable, or conditional and dynamic, the interrupt logic executing an algorithm sensitive to variables to determine the mapping. Interrupts may be external interrupts generated by devices external to the processor software (internal) interrupts generated by active streams, or conditional, based on variables. After interrupts are acknowledged streams to which interrupts or exceptions are mapped are vectored to appropriate service routines. In a synchronous method no vectoring occurs until all streams to which an interrupt is mapped acknowledge the interrupt.

US Patent:

7032226, Apr 18, 2006

Filed:

Jun 30, 2000

Appl. No.:

09/608750

Inventors:

Mario Nemirovsky - Saratoga CA, US
Narendra Sankar - Santa Clara CA, US
Adolfo Nemirovsky - San Jose CA, US
Enric Musoll - San Jose CA, US

Assignee:

MIPS Technologies, Inc. - Mountain View CA

International Classification:

G06F 9/46

US Classification:

719318, 719313, 719314, 719315, 719316, 719317, 718103, 718104, 718106, 718107, 710 22, 709213, 711147

Abstract:

A background event buffer manager (BEBM) for ordering and accounting for events in a data processing system having a processor includes a port for receiving event identifications (IDs) from a device, a queuing function enabled for queuing event IDs received, and a notification function for notifying the processor of queued event IDs. The BEBM handles all event ordering and accounting for the processor. The BEBM in preferred embodiments queues events by type with priority and by priority within type, and also handles sending acknowledgement to the device when processing on each event is concluded, and buffers the acknowledgement process. In particular embodiments the apparatus and method is taught as a packet processing router engine.

US Patent:

7043467, May 9, 2006

Filed:

Jun 2, 2000

Appl. No.:

09/586115

Inventors:

Rodolfo Milito - Los Gatos CA, US
Adolfo Nemirovsky - San Jose CA, US
Mario Nemirovsky - Los Gatos CA, US

Assignee:

MIPS Technologies, Inc. - Mountain View CA

International Classification:

G06F 17/00
G06N 5/00

US Classification:

706 45, 706 46, 706 47

Abstract:

For routing packets by rules in a packet network, a system and method in a routing device for selecting rules to apply to packets having each N fields in a header, considers rules as entities in N-dimensional space, projects the rules onto N-axes in the space, marks the beginning and ending of each projection as breakpoints, numbers intervals between breakpoints in sequential binary numbers, associates a subset of the set of rules as applicable to each interval between breakpoints on each axis, then considers a packet as a point in the N-dimensional space according to its header field values, locates the binary numbered interval into which the point projects on each axis by performing a search on each axis for the numbered interval into which the point projects on that axis, thereby determining the subset of rules applying to the packet for that axis, and determines the second set of matching rules from the subsets of rules by selecting those rules as matching the packet that apply to the packet on at least one of the N axes. Optional and enhanced methods are taught for special circumstances.

US Patent:

7058064, Jun 6, 2006

Filed:

Dec 14, 2000

Appl. No.:

09/737375

Inventors:

Mario Nemirovsky - Saratoga CA, US
Enric Musoll - San Jose CA, US
Stephen Melvin - San Francisco CA, US
Narendra Sankar - Santa Clara CA, US
Nandakumar Sampath - Santa Clara CA, US
Adolfo Nemirovsky - San Jose CA, US

Assignee:

MIPS Technologies, Inc. - Mountain View CA

International Classification:

H04L 12/56
G06F 13/00
G06F 12/00

US Classification:

3703957, 370412, 710 52, 710310, 711154, 711170

Abstract:

In a data-packet processor, a configurable queueing system for packet accounting during processing has a plurality of queues arranged in one or more clusters, an identification mechanism for creating a packet identifier for arriving packets, insertion logic for inserting packet identifiers into queues and for determining into which queue to insert a packet identifier, and selection logic for selecting packet identifiers from queues to initiate processing of identified packets, downloading of completed packets, or for requeueing of the selected packet identifiers.

US Patent:

7139898, Nov 21, 2006

Filed:

Nov 3, 2000

Appl. No.:

09/706154

Inventors:

Mario Nemirovsky - Saratoga CA, US
Adolfo Nemirovsky - San Jose CA, US
Narendra Sankar - Campbell CA, US
Enrique Musoll - San Jose CA, US

Assignee:

Mips Technologies, Inc. - Mountain View CA

International Classification:

G06F 9/312

US Classification:

712206

Abstract:

A pipelined multistreaming processor has an instruction source, a plurality of streams fetching instructions from the instruction source, a dispatch stage for selecting and dispatching instructions to a set of execution units, a set of instruction queues having one queue associated with each stream in the plurality of streams, and located in the pipeline between the instruction cache and the dispatch stage, and a select system for selecting streams in each cycle to fetch instructions from the instruction cache. The processor is characterized in that the select system selects one or more streams in each cycle for which to fetch instructions from the instruction cache, and in that the number of streams selected for which to fetch instructions in each cycle is fewer than the number of streams in the plurality of streams.