Abhinav J Tripathi

US Patent:

20080142375, Jun 19, 2008

Filed:

Sep 28, 2007

Appl. No.:

11/864254

Inventors:

Francois Doniat - Wilmington DE, US
Matthew L. Fisher - Allen TX, US
Alan D. Zdunek - Chicago IL, US
Alexandro A. Barajas - Montgomery IL, US
Ian Suni - Potsdam NY, US
Xiangfeng Chu - Potsdam NY, US
Abhinav Tripathi - Potsdam NY, US
Yuzhuo Li - Norwood NY, US

International Classification:

B23H 3/00

US Classification:

205662, 205682

Abstract:

Compositions and methods suitable for the electrochemical mechanical planarization of a conductive material layer on a semiconductor workpiece. Compositions contain a phosphonic acid based electrolyte, a corrosion inhibitor, a chelating agent, a pH adjusting agent, and a solvent as the remainder.

US Patent:

20220189976, Jun 16, 2022

Filed:

Jun 10, 2019

Appl. No.:

17/442582

Inventors:

- Santa Clara CA, US
David MEYAARD - Albuquerque NM, US
Abhinav TRIPATHI - San Jose CA, US
Liu LIU - Dalian, CN

International Classification:

H01L 27/11524
H01L 27/11551
H01L 27/11578
H01L 27/1157

Abstract:

Embodiments of the present disclosure are directed towards a memory device including a top wordline contact located in a region that is protected from erosion during a planarization process, e.g., chemical mechanical polish (CMP). In embodiments, a plurality of wordlines are formed in a stack of multiple layers and a plurality of wordline contacts are formed to intersect with the plurality of wordlines. In embodiments, the stack forms a staircase and each of the plurality of wordline contacts lands on a corresponding each of the wordlines proximate to an edge of the staircase such that a top wordline contact lands in a region on a top wordline previously covered by a sacrificial layer. In some embodiments, the region is proximate to a raised notch at an edge of the staircase. Other embodiments may be described and claimed.

US Patent:

20210143100, May 13, 2021

Filed:

Nov 12, 2019

Appl. No.:

16/681164

Inventors:

- Santa Clara CA, US
Kwame Nkrumah Eason - East Palo Alto CA, US
Abhinav Tripathi - San Jose CA, US
Ebony Lynn Mays - Morgan Hill CA, US
Jessica Sevanne Kachian - Santa Clara CA, US
Ralf Buengener - San Jose CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 23/535
H01L 27/11556
H01L 27/11582
H01L 23/522
H01L 23/528
H01L 21/768

Abstract:

A memory array including integrated word line (WL) contact structures are disclosed. The memory array comprises a plurality of WLs that includes at least a first WL and a second WL. An integrated WL contact structure includes a first WL contact and a second WL contact for the first WL and the second WL, respectively. The second WL contact extends through the first WL contact. For example, the second WL contact is nested within the first WL contact. An intervening isolation material isolates the second WL contact from the first WL contact. In an example, the second WL contact extends through a hole in the first WL to reach the second WL. The isolation material isolates the second WL contact from sidewalls of the hole in the first WL.