Aaron K Horiuchi

US Patent:

7839171, Nov 23, 2010

Filed:

May 19, 2009

Appl. No.:

12/468385

Inventors:

Tommy Miles - Fort Collins CO, US
Aaron K. Horiuchi - Thornton CO, US
Chuck P. Tung - Westford MA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H03K 19/0185
H03K 19/0175

US Classification:

326 80, 326 63, 327333

Abstract:

A digital level shifter is disclosed that receives an input voltage from a first voltage domain, and provides an output voltage to a second voltage domain. The level shifter includes transistors configured in parallel with input transistors of the level shifter in order to place the output of the level shifter in a determinate state when one of the voltage domains is placed in a low power state. Further, the level shifter includes output transistors configured to equalize a rise time slew rate and fall time slew rate, improving the reliability of the level shifter as the voltage in each voltage domain varies.

US Patent:

20060100839, May 11, 2006

Filed:

Nov 5, 2004

Appl. No.:

10/982659

Inventors:

Aaron Horiuchi - Thornton CO, US
Clark Douglas Burnside - Fort Collins CO, US
Stephen LaMar Dixon - Fort Collins CO, US
David Paul Hannum - Fort Collins CO, US
Justin Allan Coppin - Fort Collins CO, US

International Classification:

G06F 17/50

US Classification:

703014000

Abstract:

Systems and methods for implementing voltage supply noise analysis for electronic circuits are disclosed. In an exemplary embodiment a computer program product executes a computer process. The computer process generates at least one spatial profile for the electronic circuit, generates at least one temporal profile for the electronic circuit, merges the at least one temporal profile and the at least one spatial profile, and determines if the electronic circuit is operating within acceptable voltage noise margins based on the merged temporal and spatial profiles.