Xi I Li

US Patent:

7498271, Mar 3, 2009

Filed:

Jun 24, 2008

Appl. No.:

12/145035

Inventors:

Ricardo A. Donaton - Cortlandt Manor NY, US
Rashmi Jha - Wappingers Falls NY, US
Siddarth A. Krishnan - Peekskill NY, US
Xi Li - Somers NY, US
Renee T. Mo - Briarcliff Manor NY, US
Naim Moumen - Walden NY, US
Wesley C. Natzle - New Paltz NY, US
Ravikumar Ramachandran - Pleasantville NY, US
Richard S. Wise - Newburgh NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/31

US Classification:

438775, 438777, 438788, 438709, 438710

Abstract:

The present invention, in one embodiment, provides a method of forming a gate structure including providing a substrate including a semiconducting device region, a high-k dielectric material present atop the semiconducting device region, and a metal gate conductor atop the high-k dielectric material, applying a photoresist layer atop the metal gate conductor; patterning the photoresist layer to provide an etch mask overlying a portion of the metal gate conductor corresponding to a gate stack; etching the metal gate conductor and the high-k dielectric material selective to the etch mask; and removing the etch mask with a substantially oxygen free nitrogen based plasma.

US Patent:

7560387, Jul 14, 2009

Filed:

Jan 25, 2006

Appl. No.:

11/275707

Inventors:

Scott D. Allen - Dumont NJ, US
Kangguo Cheng - Beacon NY, US
Xi Li - Somers NY, US
Kevin R. Winstel - Poughkeepsie NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/311

US Classification:

438702, 438719, 438723, 438724, 257E21002

Abstract:

Methods for opening a hard mask and a silicon-on-insulator substrate in a single process chamber are disclosed. In one embodiment, the method includes patterning a photoresist over a stack including an anti-reflective coating (ARC) layer, a silicon dioxide (SiO) based hard mask layer, a silicon nitride pad layer, a silicon dioxide (SiO) pad layer and the SOI substrate, wherein the SOI substrate includes a silicon-on-insulator layer and a buried silicon dioxide (SiO) layer; and in a single process chamber: opening the ARC layer; etching the silicon dioxide (SiO) based hard mask layer; etching the silicon nitride pad layer; etching the silicon dioxide (SiO) pad layer; and etching the SOI substrate. Etching all layers in a single chamber reduces the turn-around-time, lowers the process cost, facilitates process control and/or improve a trench profile.

US Patent:

7682922, Mar 23, 2010

Filed:

Jan 18, 2007

Appl. No.:

11/624385

Inventors:

Anil K. Chinthakindi - Hay Market VA, US
Xi Li - Somers NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/20

US Classification:

438386, 438389, 438391, 438392

Abstract:

A capacitor having a suitably large value for decoupling applications is formed in a trench defined by isolation structures such as recessed isolation or shallow trench isolation. The capacitor provides a contact area coextensive with an active area and can be reliably formed individually or in small numbers. Plate contacts are preferably made through implanted regions extending to or between dopant diffused regions forming a capacitor plate. The capacitor can be formed by a process subsequent to formation of isolation structures such that preferred soft mask processes can be used to form the isolation structures and process commonality and compatibility constraint are avoided while the capacitor forming processes can be performed in common with processing for other structures.

US Patent:

7749835, Jul 6, 2010

Filed:

Mar 14, 2008

Appl. No.:

12/048263

Inventors:

Xi Li - Somers NY, US
Kangguo Cheng - Guiderland NY, US
Johnathan Faltermeier - Delanson NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/84
H01L 21/8242

US Classification:

438243, 438386, 438430, 438739, 257E21561

Abstract:

A semiconductor structure is described. The structure includes a trench opening formed in a semiconductor substrate having a semiconductor-on-insulator (SOI) layer and a buried insulating (BOX) layer; and a filling material formed in the trench opening, the filling material forming a “V” shape within the trench memory cell, wherein the “V” shape includes a top portion substantially adjacent to a top surface of the BOX layer. A method of fabricating the semiconductor structure is also described. The method includes forming a trench opening in a semiconductor substrate having an SOI layer and a BOX layer; laterally etching the BOX layer such that a portion of the trench opening associated with the BOX layer is substantially greater than a portion of the trench opening associated with the SOI layer; filling the trench opening with a filling material; and recessing the filling material.

US Patent:

7893480, Feb 22, 2011

Filed:

Jan 4, 2010

Appl. No.:

12/651608

Inventors:

Xi Li - Somers NY, US
Kangguo Cheng - Guiderland NY, US
Johnathan Faltermeier - Delanson NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 29/94
H01L 27/108

US Classification:

257301, 257304, 257350, 257E29346

Abstract:

A semiconductor structure is described. The structure includes a trench opening formed in a semiconductor substrate having a semiconductor-on-insulator (SOI) layer and a buried insulating (BOX) layer; and a filling material formed in the trench opening, the filling material forming a “V” shape within the trench memory cell, wherein the “V” shape includes a top portion substantially adjacent to a top surface of the BOX layer. A method of fabricating the semiconductor structure is also described. The method includes forming a trench opening in a semiconductor substrate having an SOI layer and a BOX layer; laterally etching the BOX layer such that a portion of the trench opening associated with the BOX layer is substantially greater than a portion of the trench opening associated with the SOI layer; filling the trench opening with a filling material; and recessing the filling material.

US Patent:

7919379, Apr 5, 2011

Filed:

Sep 10, 2007

Appl. No.:

11/852906

Inventors:

Eduard A. Cartier - New York NY, US
Rashmi Jha - Wappingers Falls NY, US
Sivananda Kanakasabapathy - Niskayuna NY, US
Xi Li - Somers NY, US
Renee T. Mo - Briarcliff Manor NY, US
Vijay Narayanan - New York NY, US
Vamsi Paruchuri - Albany NY, US
Mark T. Robson - Danbury CT, US
Kathryn T. Schonenberg - Wappingers Falls NY, US
Michelle L. Steen - Danbury CT, US
Richard Wise - Newburgh NY, US
Ying Zhang - Yorktown Heights NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/00
H01L 21/336

US Classification:

438302, 438304, 438305, 438306, 438592, 257316, 257320, 257387, 257E21202, 257E21205, 257E21444

Abstract:

The present invention relates to semiconductor devices, and more particularly to a process and structure for removing a dielectric spacer selective to a surface of a semiconductor substrate with substantially no removal of the semiconductor substrate. The method of the present invention can be integrated into a conventional CMOS processing scheme or into a conventional BiCMOS processing scheme. The method includes forming a field effect transistor on a semiconductor substrate, the FET comprising a dielectric spacer and the gate structure, the dielectric spacer located adjacent a sidewall of the gate structure and over a source/drain region in the semiconductor substrate; depositing a first nitride layer over the FET; and removing the nitride layer and the dielectric spacer selective to the semiconductor substrate with substantially no removal of the semiconductor substrate.

US Patent:

8021945, Sep 20, 2011

Filed:

Apr 14, 2009

Appl. No.:

12/423242

Inventors:

Xi Li - Somers NY, US
Russell H. Arndt - Fishkill NY, US
Kangguo Cheng - Guilderland NY, US
Richard O. Henry - Newburgh NY, US
Jinghong H. Li - Poughquag NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21/8242

US Classification:

438243, 438386, 438964

Abstract:

In accordance with an aspect of the invention, a method is provided for fabricating a semiconductor chip including a trench capacitor. In such method, a monocrystalline semiconductor region can be etched in a vertical direction through an opening in a dielectric layer to form a trench exposing a rough surface of monocrystalline semiconductor material. The trench has an initial lateral dimension in a first direction transverse to the vertical direction. The semiconductor material exposed at the surface of the trench then is etched in a crystallographic orientation-dependent manner to expose a multiplicity of crystal facets of the semiconductor material at the trench surface. A dopant-containing liner may then be deposited to line the surface of the trench and a temperature of the substrate then be elevated to drive a dopant from the dopant-containing liner into the semiconductor region adjacent to the surface. During such step, typically a portion of the semiconductor material exposed at the wall is oxidized. At least some of the oxidized portion is removed to expose a wall of an enlarged trench, along which wall a dielectric layer and conductive material are formed in order to form a trench capacitor.

US Patent:

20130193563, Aug 1, 2013

Filed:

Mar 13, 2013

Appl. No.:

13/800488

Inventors:

International Business Machines Corporation - Armonk NY, US
Xi Li - Somers NY, US
Geng Wang - Stormville NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 29/06

US Classification:

257622

Abstract:

A trench capacitor and method of fabrication are disclosed. The SOI region is doped such that a selective isotropic etch used for trench widening does not cause appreciable pullback of the SOI region, and no spacers are needed in the upper portion of the trench.