Scott A Gray

US Patent:

6948091, Sep 20, 2005

Filed:

May 2, 2002

Appl. No.:

10/137569

Inventors:

Michael W. Bartels - Phoenix AZ, US
Nicholas J. Wilt - Glendale AZ, US
Scott L. Gray - Peoria AZ, US

Assignee:

Honeywell International Inc. - Morristown NJ

International Classification:

G06F011/00

US Classification:

714 11, 714 6

Abstract:

Methods and system for facilitating a computing platform to recover quickly from transient multi-bit data failures within a run-time data memory array in a manner that is transparent to software applications executing on the computing platform. A fault-tolerant digital computing system is provided for that utilizes parallel processing lanes in a lockstep architecture. Each processing lane includes error detectors that are configured to detect multi-bit data errors in each processing lane's memory arrays. Upon detection of a multi-bit data failure, an interrupt is generated wherein control logic software responds to the interrupt and corrects the data errors in the memory array of each processing lane.

US Patent:

7512500, Mar 31, 2009

Filed:

Dec 21, 2004

Appl. No.:

11/019691

Inventors:

Nicholas J. Wilt - Glendale AZ, US
Steven R. Thompson - Phoenix AZ, US
Scott Gray - Peoria AZ, US

Assignee:

Honeywell International, Inc. - Morristow NJ

International Classification:

G06F 3/00

US Classification:

702 34, 702 35, 702182, 702183

Abstract:

A method for initializing a chain of non-initialized data collectors is disclosed. The chain of non-initialized data collectors are coupled to a controller. In a first step communication between the controller and each data collector in the chain of non-initialized collectors is disabled, except for an active non-initialized data collector, The active non-initialized collector is coupled to the controller and any remaining non-initialized data collectors. Next, the active non-initialized data collector is initialized by assigning an identification number to the active non-initialized data collectors. The active non-initialized collector becomes an initialized data collector. Then, communication is restored between the initialized data collector and a next active non-initialized data collector in the chain of non-initialized data collectors. The method repeats until all non-initialized data collectors are initialized.

US Patent:

7929431, Apr 19, 2011

Filed:

Mar 19, 2007

Appl. No.:

11/687927

Inventors:

Nicholas J Wilt - Glendale AZ, US
Scott Gray - Peoria AZ, US

Assignee:

Honeywell International Inc. - Morristown NJ

International Classification:

H04J 3/14

US Classification:

370229, 3702301, 370231, 3702351

Abstract:

A communication network is provided. The network includes a least one switch and a plurality of ports. Each port is in communication with the at least one switch. At least one of the ports is configured to introduce a time delay after each transmission of a frame based at least in part on a maximum transmission rate of the at least one port and its allocated transmission rate.

US Patent:

7933202, Apr 26, 2011

Filed:

Feb 3, 2009

Appl. No.:

12/364619

Inventors:

Scott Gray - Peoria AZ, US
Nicholas J Wilt - Glendale AZ, US

Assignee:

Honeywell International Inc. - Morristown NJ

International Classification:

H04L 12/26
G06F 15/173

US Classification:

370230, 370401, 709225, 709206, 726 13

Abstract:

Systems and methods for bounded minimal latency for network resources without synchronization are provided. In one embodiment, a method for managing data traffic between nodes in an asynchronous network comprises: receiving a data request message at a first port of network switch; storing information about the data request message in a memory at the network switch; forwarding the data request message to a producer node; receiving a data message at a second port of the network switch; determining whether the data message is responsive to the data request message; when the data message is responsive, forwarding the data message from the network switch; and when the data message is not responsive, blocking the data message from being forwarded from the network.

US Patent:

8103934, Jan 24, 2012

Filed:

Dec 21, 2007

Appl. No.:

11/963379

Inventors:

Scott L. Gray - Peoria AZ, US

Assignee:

Honeywell International Inc. - Morristown NJ

International Classification:

H03M 13/00
G11C 29/00

US Classification:

714758, 714752, 714763, 714785, 714800

Abstract:

Methods and systems are disclosed for the detection and correction of memory errors using code words with a quantity, divisible by 4, of data bits, with an equal quantity of check bits, and having the check bits and data bits interleaved. Upon execution of a memory write instruction, a processor may send a memory word to a check bit generator that generates the check bits before the code word is written to a memory unit. Upon a signal from the processor that a memory read is requested, the memory unit may send a stored code word to a syndrome bit generator to generate a syndrome vector. The syndrome vector may then be sent to a correction bit generator and an uncorrectable error detector. These units may send corrected bits and an uncorrectable error signal, respectively, to the processor.

US Patent:

8316192, Nov 20, 2012

Filed:

Oct 8, 2009

Appl. No.:

12/575709

Inventors:

Scott Gray - Peoria AZ, US
Nicholas Wilt - Glendale AZ, US

Assignee:

Honeywell International Inc. - Morristown NJ

International Classification:

G06F 12/00

US Classification:

711154, 711170, 710305

Abstract:

Systems and methods for improved multiple-port memory are provided. In one embodiment, a processing system comprises: at least one processing core; a peripheral bus; and a memory for storing digital data, the memory divided into a first and a second partition of memory segments. The memory includes a first port coupled to the peripheral bus providing read access and write access only to the first partition, wherein the first partition stores peripheral data associated with one or more peripheral components coupled to the peripheral bus; a second port coupled to the at least one processor providing read-only access to only the second partition, wherein the second partition stores executable code for the at least one processing core; and a third port coupled to the at least one processor providing read access and write access to the entire first partition and the second partition.

US Patent:

8347027, Jan 1, 2013

Filed:

Nov 5, 2009

Appl. No.:

12/612722

Inventors:

Scott Gray - Peoria AZ, US
Kevin Stover - Glendale AZ, US

Assignee:

Honeywell International Inc. - Morristown NJ

International Classification:

G06F 12/00

US Classification:

711106, 711105

Abstract:

A method for refreshing memory is provided. The method comprises determining when a first memory of a plurality of memories is not being accessed and sending a refresh opportunity command from a master refresh controller to one of a plurality of local refresh controllers when the first memory is not being accessed, wherein the one of a plurality of local refresh controllers controls only the first memory. The method further comprises determining when the first memory needs refreshing and refreshing the first memory.

US Patent:

8365024, Jan 29, 2013

Filed:

Feb 26, 2010

Appl. No.:

12/713712

Inventors:

Nicholas Wilt - Glendale AZ, US
Scott Gray - Peoria AZ, US
Mitch Fletcher - Glendale AZ, US

Assignee:

Honeywell International Inc. - Morristown NJ

International Classification:

G01R 31/28
G06F 7/02
H03M 13/00

US Classification:

714712, 714820

Abstract:

Methods and apparatus are provided for verifying the integrity of a signal transmitted across a multiple rail data bus. The method and apparatus provide for independently processing a signal by a first processor and a second processor, the first and second processors being connected in parallel thereby generating a first processed signal and a second processed signal. Each of the processed signals is split into a first component sequence and a second component sequence, the first component sequences being different from the second component sequences. It is then determined that the first component sequences are not identical and that the second component sequences are not identical. If either of the first component sequences is not identical, or if either of the second component sequences is not identical, then an error signal is transmitted to a receiving device via a first or second rail of the bus.