Risto Donald Bell

US Patent:

6678879, Jan 13, 2004

Filed:

Jun 1, 2000

Appl. No.:

09/585681

Inventors:

Alan R. Hawse - Georgetown KY
Dragomir Nikolic - Lexington KY
Jarrod V. Brooks - Lexington KY
James D. Merchant - Starkville MS
Risto D. Bell - San Jose CA

Assignee:

Cypress Semiconductor Corp. - San Jose CA

International Classification:

G06F 1750

US Classification:

716 21, 716 5

Abstract:

A design tool, comprising a pattern injection tool configured to automatically allow for the inclusion of dummy structures, differential feature sizing and/or serif addition into integrated circuit (IC) designs, in a pre-processing stage.

US Patent:

7062425, Jun 13, 2006

Filed:

Sep 30, 1999

Appl. No.:

09/410160

Inventors:

Risto D. Bell - San Jose CA, US
J. Daniel Merchant - Starkville MS, US

Assignee:

Cypress Semiconductor Corp. - San Jose CA

International Classification:

G06F 17/50
H01L 29/73
G11C 29/00

US Classification:

703 14, 703 15, 257209, 714718

Abstract:

A method of automated enumeration of one or more devices comprising the steps of (A) generating an enumeration of a plurality of fuses and (B) compiling data for each one of said plurality of fuses, wherein the data comprises (i) one or more schematic path data, (ii) one or more simulation path data and/or (iii) one or more physical location data.

US Patent:

6615393, Sep 2, 2003

Filed:

Jun 25, 2001

Appl. No.:

09/891768

Inventors:

Risto Bell - San Jose CA

Assignee:

Cypress Semiconductor Corporation - San Jose CA

International Classification:

G06F 945

US Classification:

716 5, 716 19, 430 30

Abstract:

A method and apparatus for verification of a semiconductor device design is disclosed that includes the determination of electrical distance for shapes of a design of a semiconductor device. In the present embodiment, the method includes, for each shape to be analyzed, growing from a seed disposed within a boundary shape to be analyzed. After each new growth step, a frontier edge or a frontier polygon is generated. No frontier edges or frontier polygons result from growth steps relating to boundary shapes that have fully traversed. Therefore, as each smaller shape is traversed, growth within the traversed shape is discontinued (no frontier edges or frontier polygons result). Thus, the growth regions of smaller shapes that have been traversed drop out, and are not included in subsequent growth steps, advantageously reducing memory requirements and run-time.

US Patent:

20220277126, Sep 1, 2022

Filed:

May 16, 2022

Appl. No.:

17/745814

Inventors:

- San Jose CA, US
John M. Hughes - Hartford CT, US
Lucio Lanza - Palo Alto CA, US
Mohamed K. Kassem - Carlsbad CA, US
Michael S. Wishart - Hillsborough CA, US
Rajeev Srivastava - Austin TX, US
Risto Bell - San Jose CA, US
Robert Timothy Edwards - Poolesville MD, US
Sherif Eid - Sunnyvale CA, US
Greg P. Shaurette - Tahoe City CA, US

International Classification:

G06F 30/39
G06F 30/30
G06F 30/33
G06F 30/367
G06F 30/392
G06F 30/398
G06F 30/3323
H01L 23/00

Abstract:

Systems and methods for obfuscating a circuit design are described. One of the methods includes receiving the circuit design from a user computing device. The circuit design includes a plurality of circuit components. The method further includes obfuscating each of the circuit components by transforming layout features associated with the circuit design into a generic layout feature representation. The generic layout feature representation excludes scaled representations of the layout features. The method also includes generating a visual representation of the obfuscated designs. Each of the obfuscated designs has an input port and an output port. The method further includes enabling placement of the obfuscated designs and routing between the input ports and the output ports of the obfuscated designs. The method includes generating an obfuscated integrated circuit design having a master input port, a master output port, the obfuscated designs, and the routing between the obfuscated designs.

US Patent:

20200285795, Sep 10, 2020

Filed:

May 20, 2020

Appl. No.:

16/879045

Inventors:

- San Jose CA, US
John M. Hughes - Hartford CT, US
Lucio Lanza - Palo Alto CA, US
Mohamed K. Kassem - Carlsbad CA, US
Michael S. Wishart - Hillsborough CA, US
Rajeev Srivastava - Austin TX, US
Risto Bell - San Jose CA, US
Robert Timothy Edwards - Poolesville MD, US
Sherif Eid - Sunnyvale CA, US
Greg P. Shaurette - Tahoe City CA, US

International Classification:

G06F 30/39
G06F 30/30
G06F 30/33
G06F 30/367
G06F 30/392
G06F 30/398
G06F 30/3323
H01L 23/00

Abstract:

Systems and methods for obfuscating a circuit design are described. One of the methods includes receiving the circuit design from a user computing device. The circuit design includes a plurality of circuit components. The method further includes obfuscating each of the circuit components by transforming layout features associated with the circuit design into a generic layout feature representation. The generic layout feature representation excludes scaled representations of the layout features. The method also includes generating a visual representation of the obfuscated designs. Each of the obfuscated designs has an input port and an output port. The method further includes enabling placement of the obfuscated designs and routing between the input ports and the output ports of the obfuscated designs. The method includes generating an obfuscated integrated circuit design having a master input port, a master output port, the obfuscated designs, and the routing between the obfuscated designs.

US Patent:

20200089833, Mar 19, 2020

Filed:

Sep 25, 2019

Appl. No.:

16/583170

Inventors:

- San Jose CA, US
John M. Hughes - Hartford CT, US
Lucio Lanza - Palo Alto CA, US
Mohamed K. Kassem - Carlsbad CA, US
Michael S. Wishart - Hillsborough CA, US
Rajeev Srivastava - Austin TX, US
Risto Bell - San Jose CA, US
Robert Timothy Edwards - Poolesville MD, US
Sherif Eid - Sunnyvale CA, US
Greg P. Shaurette - Tahoe City CA, US

International Classification:

G06F 17/50
H01L 23/00

Abstract:

Systems and methods for engineering integrated circuit design and development are described. A requester posts a request for an integrated circuit chip design using the systems and methods. Moreover, using design tools of the systems and methods, one or more designers generate one or more designs. The designers use computer software that is provided by the systems and methods to test the one or more designs. Moreover, the designs are independently verified by a design engineering entity or by other designers. The one or more designs are provided to a fab via the systems and methods to fabricate a prototype of an integrated circuit chip. The prototype is tested on a printed circuit board by using a test software, which is provided by the systems and methods.

US Patent:

20190392105, Dec 26, 2019

Filed:

Sep 9, 2019

Appl. No.:

16/564536

Inventors:

- San Jose CA, US
John M. Hughes - Hartford CT, US
Lucio Lanza - Palo Alto CA, US
Mohamed K. Kassem - Carlsbad CA, US
Michael S. Wishart - Hillsborough CA, US
Rajeev Srivastava - Austin TX, US
Risto Bell - San Jose CA, US
Robert Timothy Edwards - Poolesville MD, US
Sherif Eid - Sunnyvale CA, US
Greg P. Shaurette - Tahoe City CA, US

International Classification:

G06F 17/50
H01L 23/00

Abstract:

Systems and methods for obfuscating a circuit design are described. One of the methods includes receiving the circuit design from a user computing device. The circuit design includes a plurality of circuit components. The method further includes obfuscating each of the circuit components by transforming layout features associated with the circuit design into a generic layout feature representation. The generic layout feature representation excludes scaled representations of the layout features. The method also includes generating a visual representation of the obfuscated designs. Each of the obfuscated designs has an input port and an output port. The method further includes enabling placement of the obfuscated designs and routing between the input ports and the output ports of the obfuscated designs. The method includes generating an obfuscated integrated circuit design having a master input port, a master output port, the obfuscated designs, and the routing between the obfuscated designs.

US Patent:

20180011948, Jan 11, 2018

Filed:

Jun 26, 2017

Appl. No.:

15/633253

Inventors:

- San Jose CA, US
John M. Hughes - Hartford CT, US
Lucio Lanza - Palo Alto CA, US
Mohamed K. Kassem - Carlsbad CA, US
Michael S. Wishart - Hillsborough CA, US
Rajeev Srivastava - Austin TX, US
Risto Bell - San Jose CA, US
Robert Timothy Edwards - Poolesville MD, US
Sherif Eid - Sunnyvale CA, US
Greg P. Shaurette - Tahoe City CA, US

International Classification:

G06F 17/50

Abstract:

Systems and methods for engineering integrated circuit design and development are described. A requester posts a request for an integrated circuit chip design using the systems and methods. Moreover, using design tools of the systems and methods, one or more designers generate one or more designs. The designers use computer software that is provided by the systems and methods to test the one or more designs. Moreover, the designs are independently verified by a design engineering entity or by other designers. The one or more designs are provided to a fab via the systems and methods to fabricate a prototype of an integrated circuit chip. The prototype is tested on a printed circuit board by using a test software, which is provided by the systems and methods.