Richard R Sheridan

US Patent:

6660559, Dec 9, 2003

Filed:

Jun 25, 2001

Appl. No.:

09/888950

Inventors:

Ronald P. Huemoeller - Chandler AZ
Richard P. Sheridan - Gilbert AZ

Assignee:

Amkor Technology, Inc. - Chandler AZ

International Classification:

H01L 2144

US Classification:

438106, 438109, 438113, 438124, 438126

Abstract:

A chip carrier package is made by using a laser-ablatable solder mask to cover areas of conductive traces on the surface of a substrate that were left uncovered during conventional processes using photoresist. These areas of the conductive traces are uncovered by using a laser to remove overlying portions of the solder mask. If a YAG laser is used, the conductive traces are removed at the same time the solder mask ablated. However, is a CO laser is used, a conventional etching process removes the exposed portions of the traces after the solder mask is ablated.

US Patent:

7190062, Mar 13, 2007

Filed:

Jun 15, 2004

Appl. No.:

10/868244

Inventors:

Richard Peter Sheridan - Gilbert AZ, US
Ronald Patrick Huemoeller - Chandler AZ, US
David Jon Hiner - Chandler AZ, US
Sukianto Rusli - Phoenix AZ, US

Assignee:

Amkor Technology, Inc. - Chandler AZ

International Classification:

H01L 23/02

US Classification:

257686, 438109, 257713, 257666

Abstract:

A semiconductor package comprising a substrate having opposed top and bottom surfaces and a conductive pattern formed thereon. Disposed on the top surface of the substrate is a semiconductor die which is electrically connected to the conductive pattern. Also disposed on the top surface of the substrate is a leadframe which is electrically connected to the conductive pattern as well. A package body encapsulates the semiconductor die and partially encapsulates the leadframe such that a portion of the leadframe is exposed in one exterior surface of the package body, thus allowing a second semiconductor package to be stacked upon and electrically connected to the semiconductor package.

US Patent:

7501338, Mar 10, 2009

Filed:

Sep 25, 2006

Appl. No.:

11/527104

Inventors:

Ronald Patrick Huemoeller - Chandler AZ, US
David Jon Hiner - Chandler AZ, US
Sukianto Rusli - Phoenix AZ, US
Richard Sheridan - Gilbert AZ, US

Assignee:

Amkor Technology, Inc. - Chandler AZ

International Classification:

H01L 21/4763

US Classification:

438622, 438667, 257E21508, 174261

Abstract:

An integrated circuit substrate having embedded lands with etching and plating control features provides improved manufacture of a high-density and low cost mounting and interconnect structure for integrated circuits. The integrated circuit substrate is formed by generating channels in a dielectric material, adding conductive material to fill the channels and then planarizing the conductive material, so that conductors are formed beneath the surface of the dielectric material. Lands are formed with feature shapes that reduce a dimpling effect at etching and/or an over-deposit of material during plating, both due to increased current density at the relatively larger land areas. Feature shapes may be a grid formed with line sizes similar to those employed to form conductive interconnects, so that all features on the substrate have essentially the same line width. Alternatively, and in particular for circular pads such as solderball attach lands, sub-features may be radially disposed around a central circular area and connected with channels formed as interconnect lines that connect the sub-features to the central circular area. Connection of the lands may be made using vias or by other conductive channels forming electrical interconnect lines.

US Patent:

7994619, Aug 9, 2011

Filed:

Nov 1, 2006

Appl. No.:

11/555682

Inventors:

Richard P. Sheridan - Gilbert AZ, US
Eric Gongora - Chandler AZ, US
Douglas J. Mathews - Mesa AZ, US

Assignee:

Stats Chippac Ltd. - Singapore

International Classification:

H01L 23/02

US Classification:

257686, 257777, 257E25006, 438109

Abstract:

An integrated circuit package system is provided including mounting a first device on a carrier, mounting a second device over the first device and the carrier in an offset face-to-face configuration, and connecting the first device and the second device at an overlap.