Michael W Jenkins

US Patent:

6341142, Jan 22, 2002

Filed:

Dec 16, 1997

Appl. No.:

08/991715

Inventors:

Francois Ducaroir - Santa Clara CA
Karl S. Nakamura - Palo Alto CA
Michael O. Jenkins - San Jose CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H04L 516

US Classification:

375219, 375224

Abstract:

A serial data transceiver is presented which includes elements which facilitate testing using only the serial data transfer terminals of the transceiver. The serial data transceiver includes a transmitter and a receiver. The transmitter receives parallel data, converts the parallel data to a serial data stream, and transmits the serial data stream. The receiver receives a serial data stream, converts the serial data stream to parallel data, and provides the parallel data. During testing, parallel data produced by the receiver is routed to the transmitter input. In one embodiment, the transmitter includes a first router for routing parallel input data to the transmitter, and the receiver includes a second router for routing parallel output data produced by the receiver. The first router is coupled to the second router, both routers receive a test signal. When the test signal is asserted, the second router routes the parallel output data produced by the receiver to the first router, and the first router routes the parallel output data produced by the receiver to the transmitter.

US Patent:

6738248, May 18, 2004

Filed:

Oct 28, 2002

Appl. No.:

10/281811

Inventors:

Michael O. Jenkins - San Jose CA
Brett D. Hardy - Chaska MN
Prashant K. Singh - Eden Prairie MN
Donald C. Grillo - Lakeville MN
Jeffrey S. Kueng - New Brighton MN

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H02H 322

US Classification:

361111, 361 90, 361119

Abstract:

An over-voltage protected integrated circuit is provided, which includes a discharge node, an input-output pad, a signal trace, which is coupled to the input-output pad, and a pair of back-to-back diodes, which is coupled between the first signal trace and the discharge node.

US Patent:

7342977, Mar 11, 2008

Filed:

Nov 26, 2002

Appl. No.:

10/304922

Inventors:

Michael O. Jenkins - San Jose CA, US
Brett D. Hardy - Chaska MN, US
Francois Ducaroir - Santa Clara CA, US
Michael Okronglis - Bloomington MN, US

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H04L 27/00
H04L 12/50
H03M 9/00

US Classification:

375295, 341100, 341101, 370366

Abstract:

A method is provided for transmitting serial data. The method includes receiving successive transmit data words, wherein each transmit data word has a plurality of bits. Each of the plurality of bits in each transmit data word is multiplied into a multiple number of adjacent bits to form an expanded data word. Each of the expanded data words is serialized to form a serial data word stream, which is transmitted.

US Patent:

8049340, Nov 1, 2011

Filed:

Mar 22, 2006

Appl. No.:

11/277188

Inventors:

Jeffrey Hall - San Jose CA, US
Shawn Nikoukary - Santa Clara CA, US
Amar Amin - Milpitas CA, US
Michael Jenkins - San Jose CA, US

Assignee:

LSI Corporation - Milpitas CA

International Classification:

H01L 23/48

US Classification:

257777, 257E23019, 257E23151, 257758

Abstract:

An integrated circuit package substrate includes a first and an additional electrically conductive layer separated from each other by an electrically insulating layer, a contact pad formed in the first electrically conductive layer for making a direct connection between the integrated circuit package substrate and a printed circuit board, and a cutout formed in the additional electrically conductive layer wherein the cutout encloses an area that completely surrounds the contact pad for avoiding parasitic capacitance between the additional electrically conductive layer and the printed circuit board.

US Patent:

8288269, Oct 16, 2012

Filed:

Oct 4, 2011

Appl. No.:

13/252632

Inventors:

Jeffrey Hall - San Jose CA, US
Shawn Nikoukary - Santa Clara CA, US
Amar Amin - Milpitas CA, US
Michael Jenkins - San Jose CA, US

Assignee:

LSI Corporation - Milpitas CA

International Classification:

H01L 21/4763

US Classification:

438622, 257758, 257E21536

Abstract:

An integrated circuit package substrate includes a first and an additional electrically conductive layer separated from each other by an electrically insulating layer, a contact pad formed in the first electrically conductive layer for making a direct connection between the integrated circuit package substrate and a printed circuit board, and a cutout formed in the additional electrically conductive layer wherein the cutout encloses an area that completely surrounds the contact pad for avoiding parasitic capacitance between the additional electrically conductive layer and the printed circuit board.

US Patent:

8648500, Feb 11, 2014

Filed:

May 18, 2011

Appl. No.:

13/110407

Inventors:

Michael O. Jenkins - San Jose CA, US
John R. Carrel - Rockwall TX, US
Mark J. Marlett - Livermore CA, US

Assignee:

XILINX, Inc. - San Jose CA

International Classification:

H02B 1/24

US Classification:

307112, 307 82, 713300

Abstract:

In accordance with some embodiments, an integrated circuit device comprises a circuit configured to provide a sense signal representing a dynamic power requirement of the circuit to a first sense node, a first sense switch coupled between the first sense node and a first die bump, and a sense switch controller configured to provide a control signal to the first sense switch.

US Patent:

20120248569, Oct 4, 2012

Filed:

Mar 29, 2011

Appl. No.:

13/075059

Inventors:

Michael O. Jenkins - San Jose CA, US
James Karp - Saratoga CA, US
Vassili Kireev - Sunnyvale CA, US
Ephrem C. Wu - San Mateo CA, US

Assignee:

XILINX, INC. - San Jose CA

International Classification:

H01L 27/06

US Classification:

257531, 257E27026

Abstract:

An embodiment of a multichip module is disclosed. For this embodiment of a multichip module, a semiconductor die and an interposer are included. The interposer has conductive layers, dielectric layers, and a substrate. Internal interconnect structures couple the semiconductor die to the interposer. External interconnect structures are for coupling the interposer to an external device. A first inductor includes at least a portion of one or more of the conductive layers of the interposer. A first end of the first inductor is coupled to an internal interconnect structure of the internal interconnect structures. A second end of the first inductor is coupled to an external interconnect structure of the external interconnect structures.

US Patent:

55703569, Oct 29, 1996

Filed:

Jun 7, 1995

Appl. No.:

8/486541

Inventors:

Damon W. Finney - San Jose CA
Michael O. Jenkins - San Jose CA
Michael J. Rayfield - Tucson AZ

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H04J 306
H04Q 1104

US Classification:

370 859

Abstract:

A data communication system includes a phase splitting circuit to split a high speed parallel data word into a number of individual parallel data bytes, a byte multiplexor for each of the phases of a phase splitting circuit, encoding and serialization circuits for converting each byte such as an 8-bit byte to an encoded form suitable for serial transmission such as by employing the Widmer et al. 8-bit/10-bit code, transmitting each encoded byte across one of a number of serial transmission links to a receiving device where the data is deserialized and decoded to recover the original byte which is then synchronized by a byte synchronization circuit. The byte synchronization circuits are then coupled to a word synchronization circuit where the original high bandwidth data word is recovered and transmitted on an internal high speed parallel bus within the receiving device.