Michael S Wong

US Patent:

6721796, Apr 13, 2004

Filed:

Jul 22, 1999

Appl. No.:

09/358869

Inventors:

Michael K. Wong - San Mateo CA

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

G06F 1516

US Classification:

709232, 709234, 709235, 3703954, 3703957, 370412, 370413, 370415, 370417

Abstract:

Multi-level buffer system dynamically allocates storage for data units arriving at network gateway, and retrieves stored data units according to hierarchical schedule. Minimum and maximum thresholds associated with system resource and storage availability determine acceptance and storage of data units. Data units are accepted preferably if all threshold criteria are met. Threshold criteria may be determined from reserved minimum buffer length, calculated maximum buffer length, or random early discard-type algorithm applied separately to each buffer level. Optionally, buffer management applies to non-hierarchical storage systems.

US Patent:

6754216, Jun 22, 2004

Filed:

May 8, 2000

Appl. No.:

09/566602

Inventors:

Michael Wong - Fremont CA
Rajesh Nair - San Jose CA
Milan Momirov - San Francisco CA

Assignee:

Nortel Networks Limited - St. Laurent

International Classification:

H04L 1228

US Classification:

37039542, 3703957

Abstract:

A system enables a cell of data to be transmitted one time over a high speed data bus to an Ethernet switch system where it is then distributed to each of the destinations for which it is intended. A first group of buffers is for temporarily storing data that is to be delivered to only one destination. A second group of buffers is for holding the cells that are to be transmitted to a plurality of devices. In the described embodiment of the invention, the unicast and multicast cells are transmitted over the same line or bus. The invention further includes a switch processor that is formed to detect congestion within the switch fabric and to transmit a congestion rating to each device coupled to transmit and receive data through the switch fabric.

US Patent:

6808307, Oct 26, 2004

Filed:

Jan 16, 2002

Appl. No.:

10/051332

Inventors:

Mehmet Aslan - Milpitas CA
Richard Dean Henderson - Sunnyvale CA
Michael Wong - Santa Clara CA
Qing Feng Ren - San Jose CA
Chungwai Benedict Ng - Mountain View CA
Hideya Oshima - Santa Clara CA

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

G01K 701

US Classification:

374178

Abstract:

A method and apparatus improves the accuracy of temperature measurements by sampling measurements from a remote sensor, where currents of different current densities are applied to the remote sensor in a time-interleaved fashion. The remote sensor includes at least one PN junction that produces a voltage corresponding to the applied current at each instance of time, and related to the temperature of the remote sensor. By applying time-interleaved current densities to the remote sensor, adverse effects from temperature variations during the measurement are minimized. Sequences of current biases having differing current densities in a forward order are applied to the remote sensor, followed by the same sequence being applied to the remote sensor in a reverse order. Similarly, a random or pseudo-random sequence may be employed in a forward and reverse order. The application of forward and reverse sequences is utilized to minimize errors in the temperature measurement.

US Patent:

6865155, Mar 8, 2005

Filed:

May 8, 2000

Appl. No.:

09/566604

Inventors:

Michael Wong - Fremont CA, US
Rajesh Nair - San Jose CA, US
Milan Momirov - San Francisco CA, US

Assignee:

Nortel Networks Ltd. - St. Laurent

International Classification:

G08C015/00

US Classification:

370235, 370418

Abstract:

A switching system includes a switch fabric that includes groups of buffers for each port interface device that communicates with external communication devices through an Ethernet plane. The port interface device is formed to receive congestion ratings reflecting buffer usage within the switch fabric for each device coupled to transmit and receive packets through the switching fabric and to determine whether to route to the switching fabric or drop the packet based upon the congestion rating of the destination device and upon a quality of service rating for the packet.

US Patent:

6901491, May 31, 2005

Filed:

Oct 16, 2002

Appl. No.:

10/272784

Inventors:

Leslie D. Kohn - Fremont CA, US
Michael K. Wong - San Mateo CA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F012/16
G06F013/00

US Classification:

711157, 711 5, 712 10, 712 11, 712 14, 714 11, 709212, 709214, 709216

Abstract:

In one embodiment, a server is provided. The server includes multiple application processor chips. Each of the multiple application processor chips includes multiple processing cores. Multiple memories corresponding to the multiple processor chips are included. The multiple memories are configured such that one processor chip is associated with one memory. A plurality of fabric chips enabling each of the multiple application processor chips to access any of the multiple memories are included. The data associated with one of the multiple application processor chips is stored across each of the multiple memories. In one embodiment, the application processor chips include a remote direct memory access (RDMA) and striping engine. The RDMA and striping engine is configured to store data in a striped manner across the multiple memories. A method for allowing multiple processors to exchange information through horizontal scaling is also provided.

US Patent:

6938119, Aug 30, 2005

Filed:

Oct 18, 2002

Appl. No.:

10/273806

Inventors:

Leslie D. Kohn - Fremont CA, US
Kunle A. Olukotun - Stanford CA, US
Michael K. Wong - San Mateo CA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F012/00

US Classification:

711105, 711154, 711156, 713320, 713321, 713322, 713323, 713330, 713340, 713400, 713401, 713500, 713501

Abstract:

A system and method for limiting power consumption of a computer memory system. The system and method includes selecting a memory access rate. The selected memory access rate corresponds to a desired average memory power consumption rate. A first time interval is started as a current time interval. A memory system is accessed. If the memory access rate has not been exceeded, then the access is applied to the memory system. Alternatively, if the memory access rate has been exceeded, then the access is delayed until the current time interval has expired and a subsequent time interval is started as the current time interval and the access is applied to the memory system.

US Patent:

6963563, Nov 8, 2005

Filed:

May 8, 2000

Appl. No.:

09/566603

Inventors:

Michael Wong - Fremont CA, US
Rajesh Nair - San Jose CA, US
Milan Momirov - San Francisco CA, US

Assignee:

Nortel Networks Limited - St. Laurent

International Classification:

H04L012/28

US Classification:

370389, 3703957, 370428, 370412, 370446

Abstract:

The present apparatus and method of use comprises a system that enables a cell of data to be transmitted one time over a high speed data bus to an switch system where it is then distributed to each of the destinations for which it is intended. A fabric access device and a multiplex devices are each formed to have groups of buffers for buffering signals according to type. The first group of buffers is for temporarily storing data that is to be delivered to only one destination. The second group of buffers is for holding the cells that are to be transmitted to a plurality of devices. In those embodiments in which the unicast and multicast cells are transmitted over the same line or bus a parsing unit examines a field within the header portion of each cell to determine whether the cell is a unicast or multicast cell. If the cell is a unicast cell, it is temporarily stored within the unicast receive buffer set. If the cell is a multicast cell, then it is temporarily stored in the multicast buffer set.

US Patent:

7200790, Apr 3, 2007

Filed:

Jul 8, 2003

Appl. No.:

10/616269

Inventors:

Anup K. Sharma - Sunnyvale CA, US
Michael K. Wong - San Mateo CA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

H04L 1/18

US Classification:

714749, 714758

Abstract:

A microchip configured to reliably transmit data is provided. The microchip includes a memory region and a selection module configured to select a portion of the data from the memory region. An error checking module configured to calculate a value derived from the selected portion of the data is provided. A pointer region including a plurality of object pointers is included. One of the object pointers is associated with an address of the portion of the data. The object pointer associated with the address is configured to receive a signal indicating an error associated with the transmission of the data. A scheduler module in communication with each of the plurality of object pointers is provided. The scheduler module is configured to schedule re-transmission of the selected portion of the data. A system and a method for reliably transmitting data between microchips are also provided.