Luke A Miller

US Patent:

8543633, Sep 24, 2013

Filed:

Sep 24, 2010

Appl. No.:

12/889988

Inventors:

Luke A. Miller - Canastota NY, US

Assignee:

Lockheed Martin Corporation - Bethesda MD

International Classification:

G06F 7/32

US Classification:

708520, 708607

Abstract:

A modified Gram-Schmidt QR decomposition core implemented in a single field programmable gate array (FPGA) comprises a converter configured to convert a complex fixed point input to a complex floating point input, dual port memory to hold complex entries of an input matrix, normalizer programmable logic module (PLM) to compute a normalization of a column vector. A second PLM performs complex, floating point multiplication on two input matrix columns. A scheduler diverts control of the QRD processing to the normalizer PLM or the second PLM. A top level state machine communicates with scheduler and monitors processing in normalizer PLM and second PLM and communicates the completion of operations to scheduler. A complex divider computes final column for output matrix Q using floating point arithmetic. Multiplexer outputs computed values as elements of output matrix Q or R.

US Patent:

20120086472, Apr 12, 2012

Filed:

Oct 7, 2010

Appl. No.:

12/899885

Inventors:

Luke A. Miller - Canastota NY, US

Assignee:

Lockheed Martin Corporation - Bethesda MD

International Classification:

H03K 19/177

US Classification:

326 39

Abstract:

A method of calculating total power usage of a field programmable gate array (FPGA) without external components generates at least one coefficient based on a power equation and a given FPGA logic design, wherein the power equation calculates FPGA power as a function of temperature and voltage. The at least one coefficient is applied to the power equation along with internally generated temperature and voltage measurement values. The temperature measurement and the voltage measurement values are applied to the power equation with the at least one coefficient applied to calculate a power measurement based on the temperature measurement value and the voltage measurement value. The at least one coefficient is generated by taking an FPGA design and iteratively simulating the design in a power estimation tool over a range of temperature and input voltage values. A characterization data set is generated and curve fitted to the power equation to produce the at least one coefficient.