Kevin V Mccarthy

US Patent:

20210043570, Feb 11, 2021

Filed:

Aug 7, 2019

Appl. No.:

16/534027

Inventors:

- Santa Clara CA, US
Kevin MCCARTHY - Tempe AZ, US
Leigh M. TRIBOLET - Chandler AZ, US
Debendra MALLIK - Chandler AZ, US
Ravindranath V. MAHAJAN - Chandler AZ, US
Robert L. SANKMAN - Phoenix AZ, US

International Classification:

H01L 23/538
H01L 23/31
H01L 23/00
H01L 21/48
H01L 21/56
H01L 21/683

Abstract:

Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a bridge with a hybrid layer on a high-density packaging (HDP) substrate, a plurality of dies over the bridge and the HDP substrate, and a plurality of through mold vias (TMVs) on the HDP substrate. The bridge is coupled between the dies and the HDP substrate. The bridge is directly coupled to two dies of the dies with the hybrid layer, where a top surface of the hybrid layer of the bridge is directly on bottom surfaces of the dies, and where a bottom surface of the bridge is directly on a top surface of the HDP substrate. The TMVs couple the HDP substrate to the dies, and have a thickness that is substantially equal to a thickness of the bridge. The hybrid layer includes conductive pads, surface finish, and/or dielectric.

US Patent:

20210035911, Feb 4, 2021

Filed:

Jul 29, 2019

Appl. No.:

16/524748

Inventors:

- Santa Clara CA, US
Kevin MCCARTHY - Tempe AZ, US
Leigh M. TRIBOLET - Chandler AZ, US
Debendra MALLIK - Chandler AZ, US
Ravindranath V. MAHAJAN - Chandler AZ, US
Robert L. SANKMAN - Phoenix AZ, US

International Classification:

H01L 23/538
H01L 25/065
H01L 23/498
H01L 23/367
H01L 21/683
H01L 21/48
H01L 21/56
H01L 25/00
H01L 23/31
H01L 23/00

Abstract:

Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a bridge over a glass patch. The bridge is coupled to the glass patch with an adhesive layer. The semiconductor package also includes a high-density packaging (HDP) substrate over the bridge and the glass patch. The HDP substrate is conductively coupled to the glass patch with a plurality of through mold vias (TMVs). The semiconductor package further includes a plurality of dies over the HDP substrate, and a first encapsulation layer over the TMVs, the bridge, the adhesive layer, and the glass patch. The HDP substrate includes a plurality of conductive interconnects that conductively couple the dies to the bridge and glass patch. The bridge may be an embedded multi-die interconnect bridge (EMIB), where the EMIB is communicatively coupled to the dies, and the glass patch includes a plurality of through glass vias (TGVs).

US Patent:

20190363046, Nov 28, 2019

Filed:

May 24, 2018

Appl. No.:

15/988613

Inventors:

- Santa Clara CA, US
Kevin McCarthy - Tempe AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 23/498
H01L 21/48

Abstract:

Disclosed herein are integrated circuit (IC) package supports and related apparatuses and methods. For example, in some embodiments, an IC package support may include a layer of dielectric material; a conductive pad at least partially on a top surface of the layer of dielectric material; and a layer of material on side surfaces of the conductive pad, wherein the layer of material does not extend onto the top surface of the layer of dielectric material. Other embodiments are also disclosed.

US Patent:

20190304889, Oct 3, 2019

Filed:

Mar 30, 2018

Appl. No.:

15/941903

Inventors:

- Santa Clara CA, US
Chong ZHANG - Chandler AZ, US
Hongxia FENG - Chandler AZ, US
Kevin MCCARTHY - Tempe AZ, US

International Classification:

H01L 23/498
H01L 23/00
H01L 21/48
H05K 1/11
H05K 3/40
H05K 3/06

Abstract:

Techniques for fabricating a package substrate comprising a via, a conductive line, and a pad are described. The package substrate can be included in a semiconductor package. For one technique, a package substrate includes: a pad in a dielectric layer; a via; and a conductive line. The via and the conductive line can be part of a structure. Alternatively, the conductive line can be adjacent to the via. The dielectric layer can include a pocket above the pad. One or more portions of the via may be formed in the pocket above the pad. Zero or more portions of the via can be formed on the dielectric layer outside the pocket. In some scenarios, no pad is above the via. The package substrate provides several advantages. One exemplary advantage is that the package substrate can assist with increasing an input/output density per millimeter per layer (IO/mm/layer) of the package substrate.

US Patent:

20150276480, Oct 1, 2015

Filed:

Mar 29, 2014

Appl. No.:

14/229909

Inventors:

Nilanjan GHOSH - Chandler AZ, US
Kevin T. MCCARTHY - Tempe AZ, US
Zhiyong WANG - Chandler AZ, US
Deepak GOYAL - Phoenix AZ, US
Changhua LIU - Chandler AZ, US
Leonel R. ARANA - Phoenix AZ, US

International Classification:

G01J 3/28
G01J 3/04
G01J 3/44

Abstract:

Embodiments include devices, systems and processes for using a combined confocal Raman microscope for inspecting a photo resist film material layer formed on the top surface of a layer of a substrate package, to detect border defects between regions of light exposed (e.g., cured) and unexposed (e.g., uncured) resist film material. Use of the confocal Raman microscope may provide a 3D photo-resist chemical imaging and characterization technique based on combining (1) Raman spectroscopy to identify the borders between regions of light exposed and unexposed resist along XY planes, with (2) Confocal imaging to select a Z-height of the XY planes scanned. Such detection provides fast, high resolution, non-destructive in-line inspection, and improves technical development of polymerization profiles of the resist film material.