Jason Charles Brandt

US Patent:

7305592, Dec 4, 2007

Filed:

Jun 30, 2004

Appl. No.:

10/882813

Inventors:

Gilbert Neiger - Portland OR, US
Andrew V. Anderson - Hillsboro OR, US
Steven M. Bennett - Hillsboro OR, US
Jason Brandt - Austin TX, US
Erik Cota-Robles - Portland OR, US
Stalinselvaraj Jeyasingh - Beaverton OR, US
Alain Kägi - Portland OR, US
Sanjoy K. Mondal - San Marcos TX, US
Rajesh Parthasarathy - Hillsboro OR, US
Dion Rodgers - Hillsboro OR, US
Lawrence O. Smith - Beaverton OR, US
Richard A. Uhlig - Hillsboro OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 11/00

US Classification:

714 48, 714 42

Abstract:

In one embodiment, information pertaining to a first fault occurring during operation of a virtual machine (VM) is stored in a first field. A second fault is detected while delivering the first fault to the VM, and a determination is made as to whether the second fault is associated with a transition of control to a virtual machine monitor (VMM). If this determination is positive, information pertaining to the second fault is stored in a second field, and control is transitioned to the VMM.

US Patent:

7356735, Apr 8, 2008

Filed:

Mar 30, 2004

Appl. No.:

10/814569

Inventors:

Steven M. Bennett - Hillsboro OR, US
Andrew V. Anderson - Hillsboro OR, US
Erik Cota-Robles - Portland OR, US
Stalinselvaraj Jeyasingh - Beaverton OR, US
Alain Kägi - Portland OR, US
Gilbert Neiger - Portland OR, US
Richard Uhlig - Hillsboro OR, US
Sanjoy K. Mondal - San Marcos TX, US
Jason Brandt - Austin TX, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 11/00

US Classification:

714 34, 714 38, 714 45, 718 1

Abstract:

Methods and systems to provide support for single stepping a virtual machine in a virtual machine environment are disclosed. An exemplary method may include receiving a request to transition control to a virtual machine (VM) from a virtual machine monitor (VMM), determining that a single-stepping indicator is set to a single stepping value, and transitioning control to the VM. Further, if an execution of a first instruction in the VM completes successfully, control is transitioned to the VMM following the successful completion of the execution of the first instruction.

US Patent:

7552254, Jun 23, 2009

Filed:

Jul 30, 2003

Appl. No.:

10/630286

Inventors:

Robert T. George - Austin TX, US
Jason W. Brandt - Austin TX, US
Jonathan D. Combs - Austin TX, US
Peter J. Ruscito - Folsom CA, US
Sanjoy K. Mondal - San Marcos TX, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 3/00
G06F 12/00
G06F 9/26
G06F 13/00

US Classification:

710 58, 710 52, 710 55, 711169, 711205, 711206, 711207, 711208, 711209

Abstract:

In one embodiment of the present invention, an apparatus includes a pipeline resource having different address spaces each corresponding to a different address space identifier. Each address space may have entries that include data values associated with the address space identifier.

US Patent:

7552255, Jun 23, 2009

Filed:

Jul 30, 2003

Appl. No.:

10/630287

Inventors:

Robert T. George - Austin TX, US
Jason W. Brandt - Austin TX, US
K. S. Venkatraman - Hillsboro OR, US
Sangwook P. Kim - Austin TX, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 3/00
G06F 5/00
G06F 12/00
G06F 13/00

US Classification:

710 58, 710 52, 710 55, 711169, 711205, 711206, 711207, 711208, 711209

Abstract:

In one embodiment of the present invention, a method includes invalidating an entry of a filter coupled to a pipeline resource if an update to the entry occurs during a first context; and flushing a portion of the pipeline resource corresponding to an address space including the entry.

US Patent:

7562179, Jul 14, 2009

Filed:

Jul 30, 2004

Appl. No.:

10/903704

Inventors:

Jason W. Brandt - Austin TX, US
Sanjoy K. Mondal - San Marcos TX, US
Richard Uhlig - Hillsboro OR, US
Gilbert Neiger - Portland OR, US
Robert T. George - Austin TX, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 12/10

US Classification:

711 6, 711209, 718 1

Abstract:

In one embodiment of the present invention, a method includes switching between a first address space and a second address space, determining if the second address space exists in a list of address spaces; and maintaining entries of the first address space in a translation buffer after the switching. In such manner, overhead associated with such a context switch may be reduced.

US Patent:

7743233, Jun 22, 2010

Filed:

Apr 5, 2005

Appl. No.:

11/100032

Inventors:

Hong Wang - Fremont CA, US
Gautham N. Chinya - Hillsboro OR, US
Richard A. Hankins - San Jose CA, US
Shivnandan D. Kaushik - Portland OR, US
Bryant Bigbee - Scottsdale AZ, US
John Shen - San Jose CA, US
Per Hammarlund - Hillsboro OR, US
Xiang Zou - Beaverton OR, US
Jason W. Brandt - Austin TX, US
Prashant Sethi - Folsom CA, US
Douglas M. Carmean - Beaverton OR, US
Baiju V. Patel - Portland OR, US
Scott Dion Rodgers - Hillsboro OR, US
Ryan N. Rakvic - Palo Alto CA, US
John L. Reid - Portland OR, US
David K. Poulsen - Champaign IL, US
Sanjiv M. Shah - Champaign IL, US
James Paul Held - Portland OR, US
James Charles Abel - Phoenix AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 9/00

US Classification:

712220

Abstract:

Disclosed are embodiments of a system, methods and mechanism for management and translation of mapping between logical sequencer addresses and physical or logical sequencers in a multi-sequencer multithreading system. A mapping manager may manage assignment and mapping of logical sequencer addresses or pages to actual sequencers or frames of the system. Rationing logic associated with the mapping manager may take into account sequencer attributes when such mapping is performed Relocation logic associated with the mapping manager may manage spill and fill of context information to/from a backing store when re-mapping actual sequencers. Sequencers may be allocated singly, or may be allocated as part of partitioned blocks. The mapping manager may also include translation logic that provides an identifier for the mapped sequencer each time a logical sequencer address is used in a user program. Other embodiments are also described and claimed.

US Patent:

7899972, Mar 1, 2011

Filed:

Jun 12, 2009

Appl. No.:

12/483519

Inventors:

Jason W. Brandt - Austin TX, US
Sanjoy K. Mondal - San Marcos TX, US
Richard Uhlig - Hillsboro OR, US
Gilbert Neiger - Portland OR, US
Robert T. George - Austin TX, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 21/00

US Classification:

711 6, 711209, 718 1

Abstract:

In one embodiment of the present invention, a method includes switching between a first address space and a second address space, determining if the second address space exists in a list of address spaces; and maintaining entries of the first address space in a translation buffer after the switching. In such manner, overhead associated with such a context switch may be reduced.

US Patent:

7904694, Mar 8, 2011

Filed:

Mar 30, 2009

Appl. No.:

12/413655

Inventors:

Jason W. Brandt - Austin TX, US
Sanjoy K. Mondal - San Marcos TX, US
Richard Uhlig - Hillsboro OR, US
Gilbert Neiger - Portland OR, US
Robert T. George - Austin TX, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 9/22

US Classification:

711206, 712228

Abstract:

In one embodiment of the present invention, a method includes switching between a first address space and a second address space, determining if the second address space exists in a list of address spaces; and maintaining entries of the first address space in a translation buffer after the switching. In such manner, overhead associated with such a context switch may be reduced.