Imran Khan

US Patent:

20180197986, Jul 12, 2018

Filed:

Mar 8, 2018

Appl. No.:

15/915529

Inventors:

- Dallas TX, US
IMRAN KHAN - RICHARDSON TX, US
XIAOJU WU - DALLAS TX, US

International Classification:

H01L 29/78
H01L 21/762
H01L 29/06
H01L 29/66

Abstract:

A p-channel drain extended metal oxide semiconductor (DEPMOS) device includes a doped surface layer at least one nwell finger defining an nwell length and width direction within the doped surface layer. A first pwell is on one side of the nwell finger including a p+ source and a second pwell is on an opposite side of the nwell finger including a p+ drain. A gate stack defines a channel region of the nwell finger between the source and drain. A field dielectric layer is on a portion of the doped surface layer defining active area boundaries including a first active area having a first active area boundary including a first active area boundary along the width direction (WD boundary). The nwell finger includes a reduced doping finger edge region over a portion of the WD boundary.

US Patent:

20170309744, Oct 26, 2017

Filed:

Apr 21, 2016

Appl. No.:

15/135154

Inventors:

- Dallas TX, US
IMRAN KHAN - RICHARDSON TX, US
XIAOJU WU - DALLAS TX, US

International Classification:

H01L 29/78
H01L 29/06
H01L 21/762
H01L 29/66
H01L 21/762

Abstract:

A p-channel drain extended metal oxide semiconductor (DEPMOS) device includes a doped surface layer at least one nwell finger defining an nwell length and width direction within the doped surface layer. A first pwell is on one side of the nwell finger including a p+source and a second pwell is on an opposite side of the nwell finger including a p+drain. A gate stack defines a channel region of the nwell finger between the source and drain. A field dielectric layer is on a portion of the doped surface layer defining active area boundaries including a first active area having a first active area boundary including a first active area boundary along the width direction (WD boundary). The nwell finger includes a reduced doping finger edge region over a portion of the WD boundary.

US Patent:

20160079343, Mar 17, 2016

Filed:

Nov 23, 2015

Appl. No.:

14/949274

Inventors:

- Dallas TX, US
Imran Mahmood KHAN - Richardson TX, US
Richard Allen FAUST - Dallas TX, US

International Classification:

H01L 49/02
H01L 23/522
H01L 21/02
H01L 21/768
H01L 21/311

Abstract:

An integrated circuit with vias with different depths stopping on etch stop layers with different thicknesses. A method of simultaneously etching vias with different depths without causing etch damage to the material being contacted by the vias.

US Patent:

20160035890, Feb 4, 2016

Filed:

Oct 16, 2015

Appl. No.:

14/885637

Inventors:

- Dallas TX, US
Amitava CHATTERJEE - Plano TX, US
Imran Mahmood KHAN - Richardson TX, US
Kaiping LIU - Plano TX, US

International Classification:

H01L 29/78
H01L 21/8234
H01L 21/8238
H01L 29/08
H01L 27/06
H01L 29/66
H01L 29/10
H01L 21/265
H01L 27/092

Abstract:

An integrated circuit and method includes a DEMOS transistor with improved CHC reliability that has a lower resistance surface channel under the DEMOS gate that transitions to a lower resistance subsurface channel under the drain edge of the DEMOS transistor gate.

US Patent:

20150187938, Jul 2, 2015

Filed:

Dec 19, 2014

Appl. No.:

14/576693

Inventors:

- Dallas TX, US
Amitava CHATTERJEE - Plano TX, US
Imran Mahmood KHAN - Richardson TX, US
Kaiping LIU - Plano TX, US

International Classification:

H01L 29/78
H01L 27/088
H01L 29/66
H01L 21/3213
H01L 21/8238
H01L 21/8234
H01L 27/092
H01L 21/265

Abstract:

An integrated circuit and method includes a DEMOS transistor with improved CHC reliability that has a lower resistance surface channel under the DEMOS gate that transitions to a lower resistance subsurface channel under the drain edge of the DEMOS transistor gate.

US Patent:

20150170999, Jun 18, 2015

Filed:

Feb 5, 2015

Appl. No.:

14/614858

Inventors:

- Dallas TX, US
Imran Mahmood KHAN - Richardson TX, US
Richard Allen FAUST - Dallas TX, US

International Classification:

H01L 23/48
H01L 23/50
H01L 49/02

Abstract:

An integrated circuit with vias with different depths stopping on etch stop layers with different thicknesses. A method of simultaneously etching vias with different depths without causing etch damage to the material being contacted by the vias.

US Patent:

20140295631, Oct 2, 2014

Filed:

Jun 11, 2014

Appl. No.:

14/301766

Inventors:

- Dallas TX, US
Amitava CHATTERJEE - Plano TX, US
Imran Mahmood KHAN - Richardson TX, US

International Classification:

H01L 29/66

US Classification:

438239

Abstract:

An analog floating-gate electrode in an integrated circuit, and method of fabricating the same, in which trapped charge can be stored for long durations. The analog floating-gate electrode is formed in a polycrystalline silicon gate level, and includes portions serving as a transistor gate electrode, a plate of a metal-to-poly storage capacitor, and a plate of poly-to-active tunneling capacitors. A silicide-block film comprised of a layer of silicon dioxide underlying a top layer of silicon nitride blocks the formation of silicide cladding on the electrode, while other polysilicon structures in the integrated circuit, such as polysilicon-to-metal capacitors, are silicide-clad. Following silicidation, a capacitor dielectric is deposited over the remaining polysilicon structures, followed by formation of an upper metal plate.

US Patent:

20140183630, Jul 3, 2014

Filed:

Dec 27, 2013

Appl. No.:

14/142006

Inventors:

- Dallas TX, US
Amitava Chatterjee - Plano TX, US
Imran Khan - Richardson TX, US

International Classification:

H01L 29/78
H01L 29/66

US Classification:

257337, 438286

Abstract:

An integrated circuit containing a MOS transistor and a DEMOS transistor of a same polarity may be formed by implanting dopants of a same conductivity type as source/drain regions of the MOS transistor and the DEMOS transistor through a gate of the MOS transistor and through a gate of the DEMOS transistor. The implanted dopants are blocked from a drain-side edge of the DEMOS transistor gate. The implanted dopants form a drain enhancement region under the DEMOS transistor gate in a drift region of an extended drain of the DEMOS transistor.