Duy Vuong Nguyen

US Patent:

20180356998, Dec 13, 2018

Filed:

May 21, 2018

Appl. No.:

15/984547

Inventors:

- San Jose CA, US
Duy Nguyen - Fremont CA, US
Wenzhong Wu - Milpitas CA, US
Jiangpeng Li - San Jose CA, US
Yong Peng - Milpitas CA, US

International Classification:

G06F 3/06

Abstract:

A system and method of implementing distributed metadata checkpointing in a storage device. A storage device is disclosed that includes storage device that employs distributed metadata checkpointing, including: flash memory; and a controller that collects metadata checkpoints and includes: a checkpoint partitioner that partitions a metadata checkpoint into a set of segments; and a segment loader that stores each segment of the set of segments into a spare region of a corresponding different flash memory pages during a write operation of data to flash memory.

US Patent:

20180357011, Dec 13, 2018

Filed:

May 11, 2018

Appl. No.:

15/977275

Inventors:

- San Jose CA, US
Duy Nguyen - Fremont CA, US
Prathamesh Amritkar - San Jose CA, US
Qing Li - San Jose CA, US

International Classification:

G06F 3/06
G06F 12/02

Abstract:

An infrastructure, method and controller card for managing flash memory in a storage infrastructure. A system is provided that includes flash memory; and a controller that includes: an I/O request handler for handling standard read and write (R/W) operations requested from a host; a garbage collection (GC) system that performs a GC process on the flash memory in response to a threshold condition, wherein the GC process includes GC-induced R/W operations; and a scheduler that interleaves standard R/W operations with GC-induced R/W operations, wherein the scheduler calculates minimum and maximum boundaries for GC-induced R/W operations for a GC process based on an estimated GC latency.

US Patent:

20160147631, May 26, 2016

Filed:

Nov 26, 2014

Appl. No.:

14/555072

Inventors:

- Palo Alto CA, US
Duy Nguyen - Fremont CA, US
Brian James Martin - Campbell CA, US

International Classification:

G06F 11/34
H04L 29/08

Abstract:

Exemplary methods, apparatuses, and systems receive a first input/output (I/O) trace including storage addresses that were subject to a plurality of I/O requests from a first workload during a first period of time. The first I/O trace is run through a cache simulation using a plurality of simulated cache sizes. A first state of the cache simulation is stored upon completing the first I/O trace simulation. The first I/O trace is deleted in response to storing the first state. A second I/O trace including storage addresses that were subject to a plurality of I/O requests from the first workload during a second period of time is received. A cumulative miss ratio curve for the first workload is generated by loading the stored first state as a starting point for simulating the second I/O trace and running the second I/O trace through the cache simulation.

US Patent:

20160147649, May 26, 2016

Filed:

Nov 26, 2014

Appl. No.:

14/555114

Inventors:

- Palo Alto CA, US
Duy Nguyen - Fremont CA, US

International Classification:

G06F 12/02
G06F 11/30
G06F 11/34
G06F 12/08

Abstract:

Exemplary methods, apparatuses, and systems include a host computer selecting a first workload of a plurality of workloads running on the host computer to be subjected to an input/output (I/O) trace. The host computer determines whether to generate the I/O trace for the first workload for a first length of time or for a second length of time. The first length of time is shorter than the second length of time. The determination is based upon runtime history for the first workload, I/O trace history for the first workload, and/or workload type of the first workload. The host computer generates the I/O trace of the first workload for the selected length of time.

US Patent:

20160147665, May 26, 2016

Filed:

Nov 26, 2014

Appl. No.:

14/555091

Inventors:

- Palo Alto CA, US
Duy Nguyen - Fremont CA, US
Brian James Martin - Campbell CA, US
Abha Jain - Sunnyvale CA, US

International Classification:

G06F 12/08

Abstract:

Exemplary methods, apparatuses, and systems receive a first input/output (I/O) trace from a first workload and run the first I/O trace through a cache simulation to determine a first miss ratio curve (MRC) for the first workload. A second I/O trace from the first workload is received and run through the cache simulation to determine a second MRC for the first workload. First and second cache sizes corresponding to a target miss rate for the first workload are determined using the first and second MRCs. A fingerprint of each of the first and I/O traces is generated. The first cache size, the second cache size, or a combination of the first and second cache sizes is selected as a cache size for the first workload based upon a comparison of the first and second fingerprints. A recommended cache size is generated based upon the selected cache size.

US Patent:

20160150003, May 26, 2016

Filed:

Nov 26, 2014

Appl. No.:

14/555041

Inventors:

- Palo Alto CA, US
Duy Nguyen - Fremont CA, US
Brian James Martin - Campbell CA, US

International Classification:

H04L 29/08
H04L 12/26

Abstract:

Exemplary methods, apparatuses, and systems receive characteristics of a plurality of input/output (I/O) requests from a workload, including logical address distance values between I/O requests and data lengths of the plurality of I/O requests. Based upon the characteristics, a data length value representative of the data lengths of the plurality of I/O requests is determined and an access pattern of the plurality of I/O requests is determined. A notification that the first workload is suitable for a virtual storage area network environment is generated based upon the characteristics. The first workload is selected as suitable in response to determining the data length value for the data lengths of the plurality of I/O requests is less than a data length threshold and/or the access pattern of the plurality of I/O requests is more random than an access pattern threshold on the spectrum from random access to sequential access.