Douglas A Laird

US Patent:

7557605, Jul 7, 2009

Filed:

Sep 14, 2007

Appl. No.:

11/855666

Inventors:

Godfrey P. D'Souza - Santa Clara CA, US
Douglas Laird - Los Gatos CA, US
Malcolm J. Wing - Palo Alto CA, US
Colin N. Murphy - Belmont CA, US
Dana L. How - Palo Alto CA, US
Robert Yu - Newark CA, US
Jay B. Patel - Los Gatos CA, US
Ivo Dobbelaere - Los Altos CA, US
Jason Golbus - Campbell CA, US
Suresh Subramaniam - Palo Alto CA, US
Mukunda Krishnappa - Cupertino CA, US
Pohrong R. Chu - Saratoga CA, US
Dave Trossen - Santa Clara CA, US
Kevin James - Santa Clara CA, US

Assignee:

Cswitch Corporation - Santa Clara CA

International Classification:

H03K 19/173

US Classification:

326 38, 326 41, 326 47

Abstract:

A system including a plurality of programmable logic blocks, a plurality of special-purpose blocks, and a configurable high-speed mesh interconnect fabric operatively connecting the plurality of programmable logic blocks and the plurality of special-purpose blocks, where the configurable high-speed mesh interconnect fabric is configured to implement a plurality of interconnect pipeline buses spanning across the system.

US Patent:

51809370, Jan 19, 1993

Filed:

Feb 28, 1992

Appl. No.:

7/843700

Inventors:

Douglas Laird - Los Gatos CA
Godfrey P. D'Souza - Santa Clara CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H03K 5159

US Classification:

307602

Abstract:

A delay compensator circuit is disclosed to compensate for variations in temperature, supply voltage and process. A monitor circuit is further disclosed that allows the monitoring of the delay of a delay element. The delay compensator circuit and monitor circuit lend themselves easily to the ASIC design methodology since they use conventional ASIC building blocks; namely gates, memory elements and delay elements. The delay compensator and monitor use a time base to track variations in circuit parameters by monitoring the delay through a delay element (delay line or sub-circuit). Compensation may be achieved by switching delays in or out of the circuit to be compensated based on variations of temperature, voltage, and process as measured using the time base. The delay compensator permits the designer to control the output hold time independently of the output delay time. The delay compensator enables a latching device to hold the output signal for the required duration after a reference.

US Patent:

60319925, Feb 29, 2000

Filed:

Jul 5, 1996

Appl. No.:

8/678541

Inventors:

Robert F. Cmelik - Sunnyvale CA
David R. Ditzel - Los Altos Hills CA
Edmund J. Kelly - San Jose CA
Colin B. Hunter - Palo Alto CA
Douglas A. Laird - Los Gatos CA
Malcolm John Wing - Menlo Park CA
Grzegorz B. Zyner - San Jose CA

Assignee:

Transmeta Corporation - Santa Clara CA

International Classification:

G06F 945

US Classification:

395705

Abstract:

A microprocessor for a host computer designed to execute target application programs for a target computer having a target instruction set including the combination of code morphing software, and morph host processing hardware designed to execute instructions of a host instruction set, the combination of the code morphing software and the morph host processing hardware comprising means to translate a set of target instructions into instructions of a host instruction set, means to optimize the instructions of the host instruction set translated from the target application program speculating upon the occurrence of a condition, means to determine under control of the code morphing software official state of the target computer which existed at the beginning of a translation of a set of target instructions during execution of the target application program by the microprocessor, means for updating state of the target computer from state of the host computer when a set of host instructions executes in accordance with the speculation, means to detect failure of the condition during the execution of the set of host instructions, means for updating state of the host computer from state of the target computer when a set of host instructions fails to execute in accordance with the speculation, and means to translate a new set of host instructions without the speculation when a set of host instructions fails to execute in accordance with the speculation.

US Patent:

56062702, Feb 25, 1997

Filed:

Dec 16, 1994

Appl. No.:

8/357607

Inventors:

Godfrey P. D'Souza - Santa Clara CA
James F. Testa - Mountain View CA
Douglas A. Laird - Los Gatos CA
James B. Burr - Foster City CA

Assignee:

Sun Microsystems, Inc. - Mountain View CA

International Classification:

H03K 1920

US Classification:

326 98

Abstract:

A dynamic clocked inverter latch with reduced charge leakage includes a first node biasing circuit with a P-MOSFET and an N-MOSFET totem-pole-coupled between VDD and an output node, and a second node biasing circuit with another N-MOSFET and another P-MOSFET totem-pole-coupled between the output node and VSS. The first P-MOSFET receives an input data signal and the first N-MOSFET receives a clock signal and in accordance therewith together cause the output node to charge to a charged state having a charge voltage associated therewith. The second N-MOSFET also receives the input data signal while the second P-MOSFET receives the inverse of the clock signal and in accordance therewith together cause the output node to discharge to a discharged state having a discharge voltage associated therewith. During inactive states of the clock signal, the first N-MOSFET becomes reverse-biased by the output node discharge voltage, while during inactive states of the inverse clock signal, the second P-MOSFET becomes reverse-biased by the output node charge voltage, thereby virtually eliminating charge leakage to and from the output node, respectively.

US Patent:

55460224, Aug 13, 1996

Filed:

Dec 16, 1994

Appl. No.:

8/357447

Inventors:

Godfrey P. D'Souza - Santa Clara CA
Douglas A. Laird - Los Gatos CA

Assignee:

Sun Microsystems, Inc. - Mountain View CA

International Classification:

H03K 190175
H03K 19094

US Classification:

326 87

Abstract:

A static logic circuit with improved output signal levels includes a static complementary MOSFET circuit with a signal node and pull-up and pull-down amplifiers, each with at least one biasing circuit, connected thereto. The pull-up and pull-down amplifiers are connected to VDD and VSS, respectively, and receive one or more logic signals (e. g. one for an inverter and more for logic gates such as AND, OR, etc. ) and one or more bias signals and in accordance therewith provide pull-up and pull-down voltages, respectively, to the signal node. In accordance with the applied pull-up or pull-down voltage, the signal node charges to a charge state with an associated node voltage approximately equal to VDD or VSS, respectively. Each biasing circuit receives the same input logic signal as its associated pull-up or pull-down amplifier and provides thereto a bias signal approximately equal to VSS or VDD, respectively. In accordance with its input logic signal, each pull-up or pull-down amplifier together with its associated biasing circuit provides either an active current path between the signal node and VDD or VSS for applying the desired pull-up or pull-down voltage, respectively, or a leakage current path between VDD and VSS for preventing the application of an undesired pull-down or pull-up voltage during application of the desired pull-up or pull-down voltage, respectively.

US Patent:

54442966, Aug 22, 1995

Filed:

Nov 22, 1993

Appl. No.:

8/156576

Inventors:

Sunil Kaul - Fremont CA
Douglas A. Laird - Los Gatos CA

Assignee:

Sun Microsystems, Inc. - Mountain View CA

International Classification:

H05K 700

US Classification:

257686

Abstract:

A package and packaging technique for enhancing performance of critical chips within an electronic device, wherein the critical chips comprise an integrated circuit. The package includes a main package incorporating a first integrated circuit coupled to a substrate board. At least one package having a second integrated circuit is mounted to the main package in order to reduce (i) propagation delay for data to transfer between critical chips within the main package and one of the plurality of packages or between the critical chips within the plurality of packages and (ii) total footprint area. The method for implementing such a package including the steps of packaging the first and second integrated circuits and electrically coupling these integrating circuits together in a mounted position.

US Patent:

57539588, May 19, 1998

Filed:

Oct 16, 1995

Appl. No.:

8/543485

Inventors:

James B. Burr - Foster City CA
Douglas Alan Laird - Los Gatos CA

Assignee:

Sun Microsystems, Inc. - Mt. View CA

International Classification:

H01L 2976
H01L 2994
H01L 31113
H01L 31062

US Classification:

257392

Abstract:

An adjustable threshold voltage MOS device having an asymmetric pocket region is disclosed herein. The pocket region abuts one of a source or drain proximate the device's channel region. The pocket region has the same conductivity type as the device's bulk (albeit at a higher dopant concentration) and, of course, the opposite conductivity type as the device's source and drain. An MOS device having such pocket region may have its threshold voltage adjusted by applying a potential directly to its pocket region. This capability is realized by providing a contact or conductive tie electrically coupled to the pocket region. This "pocket tie" is also electrically coupled to a metallization line (external to the device) which can be held at a specified potential corresponding to a potential required to back-bias the device by a specified amount.

US Patent:

50581104, Oct 15, 1991

Filed:

May 3, 1989

Appl. No.:

7/346648

Inventors:

Robert Beach - Los Altos CA
Mark Bryers - San Jose CA
Casey Cox - Palo Alto CA
Richard Fall - Palo Alto CA
Norman Finn - San Jose CA
Douglas Laird - San Jose CA

Assignee:

Ultra Network Technologies - San Jose CA

International Classification:

H04J 302
H04J 324

US Classification:

370 856

Abstract:

A computer network method and apparatus. The present invention comprises a computer network having one or more hubs, each hub comprising one or more connection means for connection of computing devices to the network. Each connection means comprising a first interface means for coupling with a computing device, a second interface means for coupling with the network and a protocol processing means. The protocol processing means receives message packets and, depending on the message type, processing the message as either a network control message or a data transfer message. The present invention provides for "flow through" of data in the case of data transfer messages. The present invention further provides for calculation of checksum bytes as a data packet is received by the protocol processing means.