Christopher A Small

US Patent:

7487317, Feb 3, 2009

Filed:

Nov 3, 2005

Appl. No.:

11/265956

Inventors:

Alexandra Fedorova - Lincoln MA, US
Christopher A. Small - Cambridge MA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F 12/08
G06F 9/46

US Classification:

711168, 711118, 711130, 711140, 711169, 718102

Abstract:

A chip multithreading processor schedules and assigns threads to its processing cores dependent on estimated miss rates in a shared cache memory of the threads. A cache miss rate of a thread is estimated by measuring cache miss rates of one or more groups of executing threads, where at least one of the groups includes the thread of interest. Using a determined estimated cache miss rate of the thread, the thread is scheduled with other threads to achieve a relatively low cache miss rate in the shared cache memory.

US Patent:

7818747, Oct 19, 2010

Filed:

Nov 3, 2005

Appl. No.:

11/265814

Inventors:

Alexandra Fedorova - Lincoln MA, US
Christopher A. Small - Cambridge MA, US

Assignee:

Oracle America, Inc. - Redwood City CA

International Classification:

G06F 9/46
G06F 12/00
G06F 13/00
G06F 13/28

US Classification:

718102, 718107, 711 1, 711113, 711118, 711147, 711170

Abstract:

A chip multithreading processor schedules and assigns threads to its processing cores dependent on estimated miss rates in a shared cache memory of the threads. A cache miss rate of a thread is estimated by measuring cache miss rates of one or more groups of executing threads, where at least one of the groups includes the thread of interest. Using a determined estimated cache miss rate of the thread, the thread is scheduled with other threads to achieve a relatively low cache miss rate in the shared cache memory.

US Patent:

8490101, Jul 16, 2013

Filed:

Nov 29, 2004

Appl. No.:

10/999169

Inventors:

Christopher A. Small - Cambridge MA, US
Alexandra Fedorova - Lincoln MA, US
Daniel S. Nussbaum - Cambridge MA, US

Assignee:

Oracle America, Inc. - Redwood Shores CA

International Classification:

G06F 9/46

US Classification:

718103

Abstract:

A computer system includes an integrated circuit that has a plurality of processing cores fabricated therein and configured to perform operations in parallel. Each processing core is configured to process multiple threads, where a thread is assigned to one of the plurality of processing cores dependent on a cache hit rate of the thread.

US Patent:

8539491, Sep 17, 2013

Filed:

Jul 26, 2004

Appl. No.:

10/898759

Inventors:

Christopher A. Small - Cambridge MA, US
Daniel S. Nussbaum - Cambridge MA, US
Alexandra Fedorova - Lincoln MA, US

Assignee:

Oracle America, Inc. - Redwood City CA

International Classification:

G06F 9/46

US Classification:

718102

Abstract:

A thread scheduling technique for assigning multiple threads on a single integrated circuit is dependent on the CPIs of the threads. The technique attempts to balance, to the extent possible, the loads among the processing cores by assigning threads of relatively long-latency (low CPIs) with threads of relatively short-latency (high CPIs) to the same processing core.

US Patent:

20130318283, Nov 28, 2013

Filed:

May 22, 2012

Appl. No.:

13/477966

Inventors:

Christopher Small - Cambridge MA, US
Stephen M. Byan - Littleton MA, US
James F. Lentini - Woburn MA, US

Assignee:

NetApp, Inc. - Sunnyvale CA

International Classification:

G06F 12/02

US Classification:

711103, 711E12008

Abstract:

Systems and methods for efficiently using solid-state devices are provided. Some embodiments provide for a data processing system that uses a non-volatile solid-state device as a circular log, with the goal of aligning data access patterns to the underlying, hidden device implementation, in order to maximize performance. In addition, metadata can be interspersed with data in order to align data access patterns to the underlying device implementation. Multiple input/output (I/O) buffers can also be used to pipeline insertions of metadata and data into a linear log. The observed queuing behavior of the multiple I/O buffers can be used to determine when the utilization of the storage device is approaching saturation (e.g., in order to predict excessively-long response times). Then, the I/O load on the storage device may be shed when utilization approaches saturation. As a result, the overall response time of the system is improved.

US Patent:

D3357449, May 18, 1993

Filed:

Apr 29, 1991

Appl. No.:

7/692506

Inventors:

Christopher Small - Dedham MA
Jeffrey Wixon - Brockton MA

Assignee:

The Great American Rain Barrel Company, Inc. - Dedham MA

US Classification:

D34 39

US Patent:

20150373300, Dec 24, 2015

Filed:

Jun 19, 2015

Appl. No.:

14/745274

Inventors:

- Cambridge MA, US
Thomer GIL - Brookline MA, US
Christopher SMALL - Cambridge MA, US

International Classification:

H04N 5/92
G11B 20/10
G11B 27/10
H04N 5/917

Abstract:

The system provides a method and apparatus for writing a unique copy of data associated with each of a plurality of individual users, without the need for storing duplicate copies of the entire data file. The system provides for creating an unusable copy of a portion of the data that is to be shared by all users of the complete data. The system will store and optionally encrypt and/or watermark a unique copy of the remainder portion of the data for each unique user. When accessed from storage, the system will combine the shared portion with the unique remainder to reconstitute the entire file for access by the user. Deleting the unique remainder associated with a particular user makes all of the data useless to that user. In one embodiment, the system first compresses the entire data file using index frames and delta.